Merge tag 'iommu-updates-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu...

Pull iommu updates from Joerg Roedel:
 "Core Code:

   - Fix dma-iommu scatterlist length handling in the P2PDMA path

   - Extend the generic IOMMU page-table code with detailed gather
     support for more precise invalidations

   - Add pending-gather tracking to generic page-table invalidation
     handling

   - Add support for smaller virtual address sizes in the generic AMDv1
     page-table format, including KUnit coverage

   - Fix page-size bitmap calculation for smaller VA configurations

   - Rework Arm io-pgtable allocation/freeing to consistently use the
     iommu-pages API and address-conversion helpers

   - Add PCI ATS infrastructure for devices that require ATS, including
     always-on ATS handling for pre-CXL devices

  AMD IOMMU:

   - Fix several IOTLB invalidation details, including PDE handling,
     flush-all behavior, and command address encoding

   - Honor IVINFO[VASIZE] when deriving address limits

   - Fix premature loop termination in init_iommu_one()

   - Add Hygon family 18h model 4h IOAPIC support

   - Clean up legacy-mode handling, stale comments, dead IVMD
     exclusion-range code, and unused address-size macros

  Arm SMMU / Arm SMMU v3:

   - SMMUv2:
      - Device-tree binding updates for Qualcomm Hawi, Nord and Shikra
        SoCs
      - Constrain the clocks which can be specified for recent Qualcomm
        SoCs
      - Fix broken compatible string for Qualcomm prefetcher
        configuration an add new entry for the Glymur MDSS
      - Ensure SMMU is powered-up when writing context bank for Adreno
        client

   - SMMUv3:
      - Fix off-by-one in queue allocation retry loop
      - Enable hardware update of access/dirty bits from the SMMU
      - Re-jig command construction to use separate inline helpers for
        each command type

  Intel VT-d:

   - Add the PCI segment number to DMA fault messages

   - Improve support for non-PRI mode SVA

   - Ensure atomicity during context entry teardown

   - Fix RB-tree corruption in the probe error path

  RISC-V IOMMU:

   - Add NAPOT range invalidation support

   - Use detailed gather information for invalidation decisions

   - Compute the best stride for single invalidations

   - Advertise Svpbmt support to the generic page-table code

   - Add capability definitions and clean up command macro encoding

  VeriSilicon IOMMU:

   - Add a new VeriSilicon IOMMU driver

   - Add devicetree binding documentation and MAINTAINERS coverage

   - Add the RK3588 VeriSilicon IOMMU node

   - Apply small cleanups and warning fixes in the new driver

  Rockchip IOMMU:

   - Disable the fetch DTE time limit

  Apple DART:

   - Correct a stale CONFIG_PCIE_APPLE macro name in a comment"

* tag 'iommu-updates-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (66 commits)
  iommu/dma-iommu: Fix wrong scatterlist length assignment in P2PDMA path
  iommu/amd: Control INVALIDATE_IOMMU_PAGES PDE from the gather
  iommu/amd: Make CMD_INV_IOMMU_ALL_PAGES_ADDRESS match the spec
  iommu/amd: Have amd_iommu_domain_flush_pages() use last
  iommu/amd: Pass last in through to build_inv_address()
  iommu/amd: Simplify build_inv_address()
  iommu/apple-dart: correct CONFIG_PCIE_APPLE macro name in comment
  iommu/vt-d: Fix RB-tree corruption in probe error path
  iommu/vt-d: Improve IOMMU fault information
  iommu/vt-d: Remove typo from pasid_pte_config_nested()
  iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
  iommu/vt-d: Avoid WARNING in sva unbind path
  dt-bindings: arm-smmu: Correct and add constraints for Hawi, Shikra and Kaanapali
  dt-bindings: arm-smmu: Add compatible for Qualcomm Nord SoC
  iommu/amd: Don't split flush for amd_iommu_domain_flush_all()
  iommu/rockchip: disable fetch dte time limit
  iommu/arm-smmu-v3: Allow ATS to be always on
  PCI: Allow ATS to be always on for pre-CXL devices
  PCI: Add pci_ats_required() for CXL.cache capable devices
  iommu/vsi: Use list_for_each_entry()
  ...

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index a22da6671da31b77bea1a70d7a41b6b2e7548d0c,b78347a83ed99bf91692454b156def7d7db313fc..fc1fdbfd316223f8fbddfcf6cb3f1863cd8957d4
--- 1/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
--- 2/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@@ -1472,151 -1428,19 +1472,162 @@@
                clock-names = "aclk", "hclk";
                power-domains = <&power RK3588_PD_AV1>;
                resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
+               iommus = <&av1d_mmu>;
+       };
+ 
+       av1d_mmu: iommu@fdca0000 {
+               compatible = "rockchip,rk3588-av1-iommu", "verisilicon,iommu-1.2";
+               reg = <0x0 0xfdca0000 0x0 0x600>;
+               interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
+               clock-names = "core", "iface";
+               #iommu-cells = <0>;
+               power-domains = <&power RK3588_PD_AV1>;
        };
  
 +      vicap: video-capture@fdce0000 {
 +              compatible = "rockchip,rk3588-vicap";
 +              reg = <0x0 0xfdce0000 0x0 0x800>;
 +              interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
 +              clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
 +                       <&cru DCLK_VICAP>, <&cru ICLK_CSIHOST0>,
 +                       <&cru ICLK_CSIHOST1>;
 +              clock-names = "aclk", "hclk", "dclk", "iclk", "iclk1";
 +              iommus = <&vicap_mmu>;
 +              power-domains = <&power RK3588_PD_VI>;
 +              resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
 +                       <&cru SRST_D_VICAP>, <&cru SRST_CSIHOST0_VICAP>,
 +                       <&cru SRST_CSIHOST1_VICAP>,
 +                       <&cru SRST_CSIHOST2_VICAP>,
 +                       <&cru SRST_CSIHOST3_VICAP>,
 +                       <&cru SRST_CSIHOST4_VICAP>,
 +                       <&cru SRST_CSIHOST5_VICAP>;
 +              reset-names = "arst", "hrst", "drst", "irst0", "irst1",
 +                            "irst2", "irst3", "irst4", "irst5";
 +              status = "disabled";
 +
 +              ports {
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +
 +                      vicap_dvp: port@0 {
 +                              reg = <0x0>;
 +                      };
 +
 +                      vicap_mipi0: port@1 {
 +                              reg = <0x1>;
 +                      };
 +
 +                      vicap_mipi1: port@2 {
 +                              reg = <0x2>;
 +                      };
 +
 +                      vicap_mipi2: port@3 {
 +                              reg = <0x3>;
 +
 +                              vicap_mipi2_input: endpoint {
 +                                      remote-endpoint = <&csi2_output>;
 +                              };
 +                      };
 +
 +                      vicap_mipi3: port@4 {
 +                              reg = <0x4>;
 +                      };
 +
 +                      vicap_mipi4: port@5 {
 +                              reg = <0x5>;
 +
 +                              vicap_mipi4_input: endpoint {
 +                                      remote-endpoint = <&csi4_output>;
 +                              };
 +                      };
 +
 +                      vicap_mipi5: port@6 {
 +                              reg = <0x6>;
 +                      };
 +
 +                      vicap_toisp0: port@10 {
 +                              reg = <0x10>;
 +                      };
 +
 +                      vicap_toisp1: port@11 {
 +                              reg = <0x11>;
 +                      };
 +              };
 +      };
 +
 +      vicap_mmu: iommu@fdce0800 {
 +              compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
 +              reg = <0x0 0xfdce0800 0x0 0x40>, <0x0 0xfdce0900 0x0 0x40>;
 +              interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
 +              clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
 +              clock-names = "aclk", "iface";
 +              #iommu-cells = <0>;
 +              power-domains = <&power RK3588_PD_VI>;
 +              rockchip,disable-mmu-reset;
 +              status = "disabled";
 +      };
 +
 +      csi2: csi@fdd30000 {
 +              compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2";
 +              reg = <0x0 0xfdd30000 0x0 0x10000>;
 +              interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
 +                           <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>;
 +              interrupt-names = "err1", "err2";
 +              clocks = <&cru PCLK_CSI_HOST_2>;
 +              phys = <&csi_dphy0>;
 +              power-domains = <&power RK3588_PD_VI>;
 +              resets = <&cru SRST_P_CSI_HOST_2>;
 +              status = "disabled";
 +
 +              ports {
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +
 +                      csi2_in: port@0 {
 +                              reg = <0>;
 +                      };
 +
 +                      csi2_out: port@1 {
 +                              reg = <1>;
 +
 +                              csi2_output: endpoint {
 +                                      remote-endpoint = <&vicap_mipi2_input>;
 +                              };
 +                      };
 +              };
 +      };
 +
 +      csi4: csi@fdd50000 {
 +              compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2";
 +              reg = <0x0 0xfdd50000 0x0 0x10000>;
 +              interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>,
 +                           <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
 +              interrupt-names = "err1", "err2";
 +              clocks = <&cru PCLK_CSI_HOST_4>;
 +              phys = <&csi_dphy1>;
 +              power-domains = <&power RK3588_PD_VI>;
 +              resets = <&cru SRST_P_CSI_HOST_4>;
 +              status = "disabled";
 +
 +              ports {
 +                      #address-cells = <1>;
 +                      #size-cells = <0>;
 +
 +                      csi4_in: port@0 {
 +                              reg = <0>;
 +                      };
 +
 +                      csi4_out: port@1 {
 +                              reg = <1>;
 +
 +                              csi4_output: endpoint {
 +                                      remote-endpoint = <&vicap_mipi4_input>;
 +                              };
 +                      };
 +              };
 +      };
 +
        vop: vop@fdd90000 {
                compatible = "rockchip,rk3588-vop";
                reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;

diff --cc drivers/iommu/dma-iommu.c
Simple merge

diff --cc include/uapi/linux/pci_regs.h
Simple merge