clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock

The clock gpll0_out_aux acts as the parent clock for some of the NSS
(Network Subsystem) clocks.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-6-081f4956be02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c
index 6cfe4f2b28887a6766e9b609e3f035eb865bb718..35af6ffeeb85542ea5fa4592ed3230ee2cf93bad 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq5424.c
+++ b/drivers/clk/qcom/gcc-ipq5424.c
@@ -79,6 +79,20 @@ static struct clk_fixed_factor gpll0_div2 = {
        },
 };
 
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+       .offset = 0x20000,
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+       .width = 4,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "gpll0_out_aux",
+               .parent_hws = (const struct clk_hw *[]) {
+                       &gpll0.clkr.hw
+               },
+               .num_parents = 1,
+               .ops = &clk_alpha_pll_postdiv_ro_ops,
+       },
+};
+
 static struct clk_alpha_pll gpll2 = {
        .offset = 0x21000,
        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
@@ -2934,6 +2948,7 @@ static struct clk_regmap *gcc_ipq5424_clocks[] = {
        [GPLL2] = &gpll2.clkr,
        [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
        [GPLL4] = &gpll4.clkr,
+       [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq5424_resets[] = {