]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
mt76: mt7915: bring up the WA event rx queue for band1
authorFelix Fietkau <nbd@nbd.name>
Tue, 19 Jan 2021 09:34:31 +0000 (10:34 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 14 May 2021 08:50:08 +0000 (10:50 +0200)
[ Upstream commit 76027f40f5ee04bf15cde3a83af9b873c2affa28 ]

This is needed for DBDC cards to work correctly on both bands simultaneously

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/wireless/mediatek/mt76/mt76.h
drivers/net/wireless/mediatek/mt76/mt7915/dma.c
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
drivers/net/wireless/mediatek/mt76/mt7915/pci.c
drivers/net/wireless/mediatek/mt76/mt7915/regs.h

index 3e496a188bf0f262907980059be959f361b96de3..5da6b74687ed62ce93f8704b82e721637e235b2f 100644 (file)
@@ -81,6 +81,7 @@ enum mt76_rxq_id {
        MT_RXQ_MCU,
        MT_RXQ_MCU_WA,
        MT_RXQ_EXT,
+       MT_RXQ_EXT_WA,
        __MT_RXQ_MAX
 };
 
index 8c1f9c77b14f8e9400bb3d1e0303cc3322cda396..d47d8f4376c6fb1e1a5097521276f54cb484bb65 100644 (file)
@@ -286,6 +286,14 @@ int mt7915_dma_init(struct mt7915_dev *dev)
                                       rx_buf_size, MT_RX_DATA_RING_BASE);
                if (ret)
                        return ret;
+
+               /* event from WA */
+               ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT_WA],
+                                      MT7915_RXQ_MCU_WA_EXT,
+                                      MT7915_RX_MCU_RING_SIZE,
+                                      rx_buf_size, MT_RX_EVENT_RING_BASE);
+               if (ret)
+                       return ret;
        }
 
        ret = mt76_init_queues(dev);
index fe88ff24f24189af7e62be090337146680622b8c..6bfb6f1bb878bebd759c50619e5bc303d3155d29 100644 (file)
@@ -61,6 +61,7 @@ enum mt7915_rxq_id {
        MT7915_RXQ_BAND1,
        MT7915_RXQ_MCU_WM = 0,
        MT7915_RXQ_MCU_WA,
+       MT7915_RXQ_MCU_WA_EXT,
 };
 
 struct mt7915_sta_stats {
index aeb86fbea41ca898c7fa2e11f031ab8b4a3d4e43..99f11588601d5b8f51ca1fadb9d7011b6621d20f 100644 (file)
@@ -26,6 +26,7 @@ mt7915_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
                [MT_RXQ_EXT] = MT_INT_RX_DONE_DATA1,
                [MT_RXQ_MCU] = MT_INT_RX_DONE_WM,
                [MT_RXQ_MCU_WA] = MT_INT_RX_DONE_WA,
+               [MT_RXQ_EXT_WA] = MT_INT_RX_DONE_WA_EXT,
        };
 
        mt7915_irq_enable(dev, rx_irq_mask[q]);
@@ -67,6 +68,9 @@ static irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
        if (intr & MT_INT_RX_DONE_WA)
                napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
 
+       if (intr & MT_INT_RX_DONE_WA_EXT)
+               napi_schedule(&dev->mt76.napi[MT_RXQ_EXT_WA]);
+
        if (intr & MT_INT_MCU_CMD) {
                u32 val = mt76_rr(dev, MT_MCU_CMD);
 
index 848703e6eb7cea86f9b63535149076569ec3ad3d..294cc076933150021daa864f7c067b0ec6ea53c3 100644 (file)
 #define MT_INT_RX_DONE_DATA1           BIT(17)
 #define MT_INT_RX_DONE_WM              BIT(0)
 #define MT_INT_RX_DONE_WA              BIT(1)
-#define MT_INT_RX_DONE_ALL             (BIT(0) | BIT(1) | GENMASK(17, 16))
+#define MT_INT_RX_DONE_WA_EXT          BIT(2)
+#define MT_INT_RX_DONE_ALL             (GENMASK(2, 0) | GENMASK(17, 16))
 #define MT_INT_TX_DONE_MCU_WA          BIT(15)
 #define MT_INT_TX_DONE_FWDL            BIT(26)
 #define MT_INT_TX_DONE_MCU_WM          BIT(27)