crypto: octeontx2 - Use dynamic allocated memory region for lmtst

Current driver uses static LMTST region allocated by firmware.
Firmware allocated memory for LMTST is available in PF/VF BAR2.
Using this memory have performance impact as this is mapped as
device memory. There is another option to allocate contiguous
memory at run time and map this in LMT MAP table with the
help of AF driver. With this patch dynamic allocated memory
is used for LMTST.

Also add myself as maintainer for crypto octeontx2 driver

Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/MAINTAINERS b/MAINTAINERS
index b951660f0990516cdc74a961894e6a68c2dc6113..85f7619e06b62a131baf7fa3b1dc63255a674bba 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14290,6 +14290,7 @@ F:      include/uapi/drm/armada_drm.h
 
 MARVELL CRYPTO DRIVER
 M:     Srujana Challa <schalla@marvell.com>
+M:     Bharat Bhushan <bbhushan2@marvell.com>
 L:     linux-crypto@vger.kernel.org
 S:     Maintained
 F:     drivers/crypto/marvell/

diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c
index 5cae8fafa15189ff61449fd2663294c49e7623e7..d4aab9e20f2a8ff1c1b1b9aa259a031e5da018c7 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c
+++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c
@@ -6,6 +6,7 @@
 #include "otx2_cptvf.h"
 #include "otx2_cptlf.h"
 #include "cn10k_cpt.h"
+#include "otx2_cpt_common.h"
 
 static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
                               struct otx2_cptlf_info *lf);
@@ -27,7 +28,7 @@ static struct cpt_hw_ops cn10k_hw_ops = {
 static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
                               struct otx2_cptlf_info *lf)
 {
-       void __iomem *lmtline = lf->lmtline;
+       void *lmtline = lf->lfs->lmt_info.base + (lf->slot * LMTLINE_SIZE);
        u64 val = (lf->slot & 0x7FF);
        u64 tar_addr = 0;
 
@@ -41,15 +42,49 @@ static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,
        dma_wmb();
 
        /* Copy CPT command to LMTLINE */
-       memcpy_toio(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
+       memcpy(lmtline, cptinst, insts_num * OTX2_CPT_INST_SIZE);
        cn10k_lmt_flush(val, tar_addr);
 }
 
+void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs)
+{
+       struct otx2_lmt_info *lmt_info = &lfs->lmt_info;
+
+       if (!lmt_info->base)
+               return;
+
+       dma_free_attrs(&pdev->dev, lmt_info->size,
+                      lmt_info->base - lmt_info->align,
+                      lmt_info->iova - lmt_info->align,
+                      DMA_ATTR_FORCE_CONTIGUOUS);
+}
+EXPORT_SYMBOL_NS_GPL(cn10k_cpt_lmtst_free, "CRYPTO_DEV_OCTEONTX2_CPT");
+
+static int cn10k_cpt_lmtst_alloc(struct pci_dev *pdev,
+                                struct otx2_cptlfs_info *lfs, u32 size)
+{
+       struct otx2_lmt_info *lmt_info = &lfs->lmt_info;
+       dma_addr_t align_iova;
+       dma_addr_t iova;
+
+       lmt_info->base = dma_alloc_attrs(&pdev->dev, size, &iova, GFP_KERNEL,
+                                        DMA_ATTR_FORCE_CONTIGUOUS);
+       if (!lmt_info->base)
+               return -ENOMEM;
+
+       align_iova = ALIGN((u64)iova, LMTLINE_ALIGN);
+       lmt_info->iova = align_iova;
+       lmt_info->align = align_iova - iova;
+       lmt_info->size = size;
+       lmt_info->base += lmt_info->align;
+       return 0;
+}
+
 int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)
 {
        struct pci_dev *pdev = cptpf->pdev;
-       resource_size_t size;
-       u64 lmt_base;
+       u32 size;
+       int ret;
 
        if (!test_bit(CN10K_LMTST, &cptpf->cap_flag)) {
                cptpf->lfs.ops = &otx2_hw_ops;
@@ -57,18 +92,19 @@ int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf)
        }
 
        cptpf->lfs.ops = &cn10k_hw_ops;
-       lmt_base = readq(cptpf->reg_base + RVU_PF_LMTLINE_ADDR);
-       if (!lmt_base) {
-               dev_err(&pdev->dev, "PF LMTLINE address not configured\n");
-               return -ENOMEM;
+       size = OTX2_CPT_MAX_VFS_NUM * LMTLINE_SIZE + LMTLINE_ALIGN;
+       ret = cn10k_cpt_lmtst_alloc(pdev, &cptpf->lfs, size);
+       if (ret) {
+               dev_err(&pdev->dev, "PF-%d LMTLINE memory allocation failed\n",
+                       cptpf->pf_id);
+               return ret;
        }
-       size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
-       size -= ((1 + cptpf->max_vfs) * MBOX_SIZE);
-       cptpf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, lmt_base, size);
-       if (!cptpf->lfs.lmt_base) {
-               dev_err(&pdev->dev,
-                       "Mapping of PF LMTLINE address failed\n");
-               return -ENOMEM;
+
+       ret = otx2_cpt_lmtst_tbl_setup_msg(&cptpf->lfs);
+       if (ret) {
+               dev_err(&pdev->dev, "PF-%d: LMTST Table setup failed\n",
+               cptpf->pf_id);
+               cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);
        }
 
        return 0;
@@ -78,18 +114,25 @@ EXPORT_SYMBOL_NS_GPL(cn10k_cptpf_lmtst_init, "CRYPTO_DEV_OCTEONTX2_CPT");
 int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)
 {
        struct pci_dev *pdev = cptvf->pdev;
-       resource_size_t offset, size;
+       u32 size;
+       int ret;
 
        if (!test_bit(CN10K_LMTST, &cptvf->cap_flag))
                return 0;
 
-       offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
-       size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
-       /* Map VF LMILINE region */
-       cptvf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, offset, size);
-       if (!cptvf->lfs.lmt_base) {
-               dev_err(&pdev->dev, "Unable to map BAR4\n");
-               return -ENOMEM;
+       size = cptvf->lfs.lfs_num * LMTLINE_SIZE + LMTLINE_ALIGN;
+       ret = cn10k_cpt_lmtst_alloc(pdev, &cptvf->lfs, size);
+       if (ret) {
+               dev_err(&pdev->dev, "VF-%d LMTLINE memory allocation failed\n",
+                       cptvf->vf_id);
+               return ret;
+       }
+
+       ret = otx2_cpt_lmtst_tbl_setup_msg(&cptvf->lfs);
+       if (ret) {
+               dev_err(&pdev->dev, "VF-%d: LMTST Table setup failed\n",
+                       cptvf->vf_id);
+               cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);
        }
 
        return 0;

diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h
index 92be3ecf570fc34976c4f001a4a6617482c9ea9e..ea5990048c21608232d949fe340326f8dbb660c2 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h
+++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h
@@ -50,6 +50,7 @@ static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)
 
 int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);
 int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);
+void cn10k_cpt_lmtst_free(struct pci_dev *pdev, struct otx2_cptlfs_info *lfs);
 void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval);
 int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,
                          struct cn10k_cpt_errata_ctx *er_ctx);

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
index 84f2bb0ca11c352326978f4a90dfd957acfd8e7d..d529bcb03775f8e183bc293b0fe097072b6f4094 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
@@ -209,5 +209,6 @@ int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
 int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
 int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);
 int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot);
+int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs);
 
 #endif /* __OTX2_CPT_COMMON_H */

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c b/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
index b8b7c8a3c0ca567e3dc27820f7bb2ff86bd2a98b..95f3de3a34eb1ede50bc32e8610bfd5b9c696e0e 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
@@ -255,3 +255,28 @@ int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot)
        return ret;
 }
 EXPORT_SYMBOL_NS_GPL(otx2_cpt_lf_reset_msg, "CRYPTO_DEV_OCTEONTX2_CPT");
+
+int otx2_cpt_lmtst_tbl_setup_msg(struct otx2_cptlfs_info *lfs)
+{
+       struct otx2_mbox *mbox = lfs->mbox;
+       struct pci_dev *pdev = lfs->pdev;
+       struct lmtst_tbl_setup_req *req;
+
+       req = (struct lmtst_tbl_setup_req *)
+              otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
+                                      sizeof(struct msg_rsp));
+       if (!req) {
+               dev_err(&pdev->dev, "RVU MBOX failed to alloc message.\n");
+               return -EFAULT;
+       }
+
+       req->hdr.id = MBOX_MSG_LMTST_TBL_SETUP;
+       req->hdr.sig = OTX2_MBOX_REQ_SIG;
+       req->hdr.pcifunc = 0;
+
+       req->use_local_lmt_region = true;
+       req->lmt_iova = lfs->lmt_info.iova;
+
+       return otx2_cpt_send_mbox_msg(mbox, pdev);
+}
+EXPORT_SYMBOL_NS_GPL(otx2_cpt_lmtst_tbl_setup_msg, "CRYPTO_DEV_OCTEONTX2_CPT");

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.c b/drivers/crypto/marvell/octeontx2/otx2_cptlf.c
index b5d66afcc030b3f0c15681d71d5d0a70f3f2c783..dc7c7a2650a598f1f7ac0e5cd26b2a29fe2ec45f 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.c
@@ -433,10 +433,7 @@ int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri,
        for (slot = 0; slot < lfs->lfs_num; slot++) {
                lfs->lf[slot].lfs = lfs;
                lfs->lf[slot].slot = slot;
-               if (lfs->lmt_base)
-                       lfs->lf[slot].lmtline = lfs->lmt_base +
-                                               (slot * LMTLINE_SIZE);
-               else
+               if (!lfs->lmt_info.base)
                        lfs->lf[slot].lmtline = lfs->reg_base +
                                OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_LMT, slot,
                                                 OTX2_CPT_LMT_LF_LMTLINEX(0));

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
index bd8604be2952a9701194a0586defb555deebf4e4..6e004a5568d8862648b4b5ca789f22c0c34c43c3 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
@@ -105,11 +105,19 @@ struct cpt_hw_ops {
                              gfp_t gfp);
 };
 
+#define LMTLINE_SIZE  128
+#define LMTLINE_ALIGN 128
+struct otx2_lmt_info {
+       void *base;
+       dma_addr_t iova;
+       u32 size;
+       u8 align;
+};
+
 struct otx2_cptlfs_info {
        /* Registers start address of VF/PF LFs are attached to */
        void __iomem *reg_base;
-#define LMTLINE_SIZE  128
-       void __iomem *lmt_base;
+       struct otx2_lmt_info lmt_info;
        struct pci_dev *pdev;   /* Device LFs are attached to */
        struct otx2_cptlf_info lf[OTX2_CPT_MAX_LFS_NUM];
        struct otx2_mbox *mbox;

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
index 687b6c7d7674621b87fca8342b231d9323623206..1c5c262af48d731e0d861a91c4ffbf9fcf2c7e1a 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
@@ -792,19 +792,19 @@ static int otx2_cptpf_probe(struct pci_dev *pdev,
        cptpf->max_vfs = pci_sriov_get_totalvfs(pdev);
        cptpf->kvf_limits = 1;
 
-       err = cn10k_cptpf_lmtst_init(cptpf);
+       /* Initialize CPT PF device */
+       err = cptpf_device_init(cptpf);
        if (err)
                goto unregister_intr;
 
-       /* Initialize CPT PF device */
-       err = cptpf_device_init(cptpf);
+       err = cn10k_cptpf_lmtst_init(cptpf);
        if (err)
                goto unregister_intr;
 
        /* Initialize engine groups */
        err = otx2_cpt_init_eng_grps(pdev, &cptpf->eng_grps);
        if (err)
-               goto unregister_intr;
+               goto free_lmtst;
 
        err = sysfs_create_group(&dev->kobj, &cptpf_sysfs_group);
        if (err)
@@ -820,6 +820,8 @@ sysfs_grp_del:
        sysfs_remove_group(&dev->kobj, &cptpf_sysfs_group);
 cleanup_eng_grps:
        otx2_cpt_cleanup_eng_grps(pdev, &cptpf->eng_grps);
+free_lmtst:
+       cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);
 unregister_intr:
        cptpf_disable_afpf_mbox_intr(cptpf);
 destroy_afpf_mbox:
@@ -854,6 +856,8 @@ static void otx2_cptpf_remove(struct pci_dev *pdev)
        cptpf_disable_afpf_mbox_intr(cptpf);
        /* Destroy AF-PF mbox */
        cptpf_afpf_mbox_destroy(cptpf);
+       /* Free LMTST memory */
+       cn10k_cpt_lmtst_free(pdev, &cptpf->lfs);
        pci_set_drvdata(pdev, NULL);
 }
 

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
index 3eb45bb91296b6a2075f3aeb7c6c0174b82c64ae..12c0e966fa65feb98d4c47e42482a103b905eb27 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
@@ -502,6 +502,7 @@ static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf,
        case MBOX_MSG_CPT_INLINE_IPSEC_CFG:
        case MBOX_MSG_NIX_INLINE_IPSEC_CFG:
        case MBOX_MSG_CPT_LF_RESET:
+       case MBOX_MSG_LMTST_TBL_SETUP:
                break;
 
        default:

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
index 11e351a48efee7a44e5e72ac8f137c41cf8ee560..56904bdfd6e82bb8fb63730acd361ce94630414c 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
@@ -376,10 +376,6 @@ static int otx2_cptvf_probe(struct pci_dev *pdev,
 
        otx2_cpt_set_hw_caps(pdev, &cptvf->cap_flag);
 
-       ret = cn10k_cptvf_lmtst_init(cptvf);
-       if (ret)
-               goto clear_drvdata;
-
        /* Initialize PF<=>VF mailbox */
        ret = cptvf_pfvf_mbox_init(cptvf);
        if (ret)
@@ -405,13 +401,19 @@ static int otx2_cptvf_probe(struct pci_dev *pdev,
        if (cptvf->eng_caps[OTX2_CPT_SE_TYPES] & BIT_ULL(35))
                cptvf->lfs.ops->cpt_sg_info_create = cn10k_sgv2_info_create;
 
+       ret = cn10k_cptvf_lmtst_init(cptvf);
+       if (ret)
+               goto unregister_interrupts;
+
        /* Initialize CPT LFs */
        ret = cptvf_lf_init(cptvf);
        if (ret)
-               goto unregister_interrupts;
+               goto free_lmtst;
 
        return 0;
 
+free_lmtst:
+       cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);
 unregister_interrupts:
        cptvf_disable_pfvf_mbox_intrs(cptvf);
 destroy_pfvf_mbox:
@@ -435,6 +437,8 @@ static void otx2_cptvf_remove(struct pci_dev *pdev)
        cptvf_disable_pfvf_mbox_intrs(cptvf);
        /* Destroy PF-VF mbox */
        cptvf_pfvf_mbox_destroy(cptvf);
+       /* Free LMTST memory */
+       cn10k_cpt_lmtst_free(pdev, &cptvf->lfs);
        pci_set_drvdata(pdev, NULL);
 }
 

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
index d9fa5f6e204d2e01af8e35d5fef920b831819011..931b72580fd9f8c1f2f4ce25626007d4c0f2ce5e 100644 (file)
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
@@ -134,6 +134,7 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf,
                       sizeof(cptvf->eng_caps));
                break;
        case MBOX_MSG_CPT_LF_RESET:
+       case MBOX_MSG_LMTST_TBL_SETUP:
                break;
        default:
                dev_err(&cptvf->pdev->dev, "Unsupported msg %d received.\n",