accel/amdxdna: Fix incorrect DPM level after suspend/resume

The suspend routine sets the DPM level to 0, which unintentionally
overwrites the previously saved DPM level. As a result, the device always
resumes with DPM level 0 instead of restoring the original value.

Fix this by ensuring the suspend path does not overwrite the saved DPM
level, allowing the correct DPM level to be restored during resume.

Fixes: f4d7b8a6bc8c ("accel/amdxdna: Enhance power management settings")
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20260204171048.3165580-1-lizhi.hou@amd.com

diff --git a/drivers/accel/amdxdna/aie2_pm.c b/drivers/accel/amdxdna/aie2_pm.c
index afcd6d4683e562453d30f1d04c9ec0aca8faeb3a..579b8be13b1804519c391b805206129df7a4fd6e 100644 (file)
--- a/drivers/accel/amdxdna/aie2_pm.c
+++ b/drivers/accel/amdxdna/aie2_pm.c
@@ -36,6 +36,8 @@ int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
                return ret;
 
        ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
+       if (!ret)
+               ndev->dpm_level = dpm_level;
        amdxdna_pm_suspend_put(ndev->xdna);
 
        return ret;
@@ -65,6 +67,7 @@ int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
        ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->max_dpm_level);
        if (ret)
                return ret;
+       ndev->dpm_level = ndev->max_dpm_level;
 
        ret = aie2_pm_set_clk_gating(ndev, AIE2_CLK_GATING_ENABLE);
        if (ret)

diff --git a/drivers/accel/amdxdna/aie2_smu.c b/drivers/accel/amdxdna/aie2_smu.c
index 2d195e41f83ddd88fcc4abb85935b16fc3bd4989..d8c31924e501ba71f7ffe57dff175d49f0870b89 100644 (file)
--- a/drivers/accel/amdxdna/aie2_smu.c
+++ b/drivers/accel/amdxdna/aie2_smu.c
@@ -84,7 +84,6 @@ int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
        }
 
        ndev->hclk_freq = freq;
-       ndev->dpm_level = dpm_level;
        ndev->max_tops = 2 * ndev->total_col;
        ndev->curr_tops = ndev->max_tops * freq / 1028;
 
@@ -114,7 +113,6 @@ int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
 
        ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
        ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
-       ndev->dpm_level = dpm_level;
        ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->max_dpm_level);
        ndev->curr_tops = NPU4_DPM_TOPS(ndev, dpm_level);