]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290
authorHoratiu Vultur <horatiu.vultur@microchip.com>
Wed, 19 Nov 2025 13:47:50 +0000 (14:47 +0100)
committerClaudiu Beznea <claudiu.beznea@tuxon.dev>
Tue, 30 Dec 2025 15:11:17 +0000 (17:11 +0200)
The problem is that the MDIO controller can't detect any of the PHYs.
The reason is that the lan966x is not pulling high the GPIO 53 that is
connected to the PHYs reset GPIO. Without doing this the PHYs are kept
in reset. The mdio controller framework has the possibility to control a
GPIO to release the reset of the PHYs. So take advantage of this and set
line to be high before accessing the PHYs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20251119134750.394655-1-horatiu.vultur@microchip.com
[claudiu.beznea: add microchip in patch title, s/possiblity/possibility
 in patch description]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
arch/arm/boot/dts/microchip/lan966x-pcb8290.dts

index 3b7577e48b46704e2fa083741e63c40a519c9f05..50bd29572f3ede41c747d6bb37dfb0ac0455116b 100644 (file)
@@ -54,6 +54,7 @@
 &mdio0 {
        pinctrl-0 = <&miim_a_pins>;
        pinctrl-names = "default";
+       reset-gpios = <&gpio 53 GPIO_ACTIVE_LOW>;
        status = "okay";
 
        ext_phy0: ethernet-phy@7 {