arm64: zynqmp: Disable coresight by default

[ Upstream commit 0e3f9140ad04dca9a6a93dd6a6decdc53fd665ca ]

When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7e308b8efe977c4912079b4d1b1ab3d24908559e.1756799774.git.michal.simek@amd.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index e11d282462bd3d65f577ca0ab4a31afc50e27a7c..23d867c03263d062ab3085912c529acd8f740a16 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -550,6 +550,7 @@
                        reg = <0x0 0xfec10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu0>;
+                       status = "disabled";
                };
 
                cpu1_debug: debug@fed10000 {
@@ -557,6 +558,7 @@
                        reg = <0x0 0xfed10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu1>;
+                       status = "disabled";
                };
 
                cpu2_debug: debug@fee10000 {
@@ -564,6 +566,7 @@
                        reg = <0x0 0xfee10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu2>;
+                       status = "disabled";
                };
 
                cpu3_debug: debug@fef10000 {
@@ -571,6 +574,7 @@
                        reg = <0x0 0xfef10000 0x0 0x1000>;
                        clock-names = "apb_pclk";
                        cpu = <&cpu3>;
+                       status = "disabled";
                };
 
                /* GDMA */