RISC-V: Combine vec_duplicate + vmslt.vv to vmslt.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vmslt.wv to the
vmslt.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have asm code like below, GR2VR cost is 0.

Before this patch:
  11       beq a3,zero,.L8
  12       vsetvli a5,zero,e32,m1,ta,ma
  13       vmv.v.x v2,a2
  ...
  16   .L3:
  17       vsetvli a5,a3,e32,m1,ta,ma
  ...
  22       vmslt.vv v1,v2,v3
  ...
  25       bne a3,zero,.L3

After this patch:
  11       beq a3,zero,.L8
  ...
  14    .L3:
  15       vsetvli a5,a3,e32,m1,ta,ma
  ...
  20       vmslt.vx v1,a2,v3
  ...
  23       bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/predicates.md: Append operator lt to
	the comparison_swappable_operator.
	* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Add
	swappable operator lt handing.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 3cc954e10cc6173cf6d3fac2c02a02a871f14891..5b44165ec993ae943f111d210ee44f77aa3882a3 100644 (file)
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -612,7 +612,7 @@
   (match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
 
 (define_predicate "comparison_swappable_operator"
-  (match_code "gtu"))
+  (match_code "gtu,gt"))
 
 (define_predicate "ge_operator"
   (match_code "ge,geu"))

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index fbf2e7a5c4648c4bc57f7007cec731026c2f354d..f3c44313967cd3662400d9734dfca19efe77983c 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5917,6 +5917,8 @@ get_swapped_cmp_rtx_code (rtx_code code)
     {
     case GTU:
       return LTU;
+    case GT:
+      return LT;
     default:
       gcc_unreachable ();
     }