.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
.apmg_not_supported = true,
.mac_addr_from_csr = 0x380,
- .min_umac_error_event_table = 0x400000,
.d3_debug_data_base_addr = 0x401000,
.d3_debug_data_length = 60 * 1024,
.mon_smem_regs = {
.smem_offset = IWL8260_SMEM_OFFSET,
.smem_len = IWL8260_SMEM_LEN,
.apmg_not_supported = true,
- .min_umac_error_event_table = 0x800000,
};
static const struct iwl_tt_params iwl8000_tt_params = {
.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
.apmg_not_supported = true,
.mac_addr_from_csr = 0x380,
- .min_umac_error_event_table = 0x800000,
.d3_debug_data_base_addr = 0x401000,
.d3_debug_data_length = 92 * 1024,
.nvm_hw_section_num = 10,
.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
.apmg_not_supported = true,
.mac_addr_from_csr = 0x380,
- .min_umac_error_event_table = 0x400000,
.d3_debug_data_base_addr = 0x401000,
.d3_debug_data_length = 60 * 1024,
.mon_smem_regs = {
.smem_len = IWL_BZ_SMEM_LEN,
.apmg_not_supported = true,
.mac_addr_from_csr = 0x30,
- .min_umac_error_event_table = 0xD0000,
.d3_debug_data_base_addr = 0x401000,
.d3_debug_data_length = 60 * 1024,
.mon_smem_regs = {
.smem_len = IWL_DR_SMEM_LEN,
.apmg_not_supported = true,
.mac_addr_from_csr = 0x30,
- .min_umac_error_event_table = 0xD0000,
.d3_debug_data_base_addr = 0x401000,
.d3_debug_data_length = 60 * 1024,
.mon_smem_regs = {
.smem_len = IWL_SC_SMEM_LEN,
.apmg_not_supported = true,
.mac_addr_from_csr = 0x30,
- .min_umac_error_event_table = 0xD0000,
.d3_debug_data_base_addr = 0x401000,
.d3_debug_data_length = 60 * 1024,
.mon_smem_regs = {
* for aggregation
* @min_txq_size: minimum number of slots required in a TX queue
* @gp2_reg_addr: GP2 (timer) register address
- * @min_umac_error_event_table: minimum SMEM location of UMAC error table
* @mon_dbgi_regs: monitor DBGI registers
* @mon_dram_regs: monitor DRAM registers
* @mon_smem_regs: monitor SMEM registers
netdev_features_t features;
u32 smem_offset;
u32 smem_len;
- u32 min_umac_error_event_table;
u32 d3_debug_data_base_addr;
u32 d3_debug_data_length;
u32 min_txq_size;
umac_error_table = le32_to_cpu(umac->dbg_ptrs.error_info_addr) &
~FW_ADDR_CACHE_CONTROL;
- if (umac_error_table >= trans->mac_cfg->base->min_umac_error_event_table)
- iwl_fw_umac_set_alive_err_table(trans, umac_error_table);
- else
- IWL_ERR(mld, "Not valid error log pointer 0x%08X\n",
- umac_error_table);
+ iwl_fw_umac_set_alive_err_table(trans, umac_error_table);
alive_data->valid = status == IWL_ALIVE_STATUS_OK;
~FW_ADDR_CACHE_CONTROL;
if (umac_error_table) {
- if (umac_error_table >=
- mvm->trans->mac_cfg->base->min_umac_error_event_table) {
- iwl_fw_umac_set_alive_err_table(mvm->trans,
- umac_error_table);
- } else {
- IWL_ERR(mvm,
- "Not valid error log pointer 0x%08X for %s uCode\n",
- umac_error_table,
- (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) ?
- "Init" : "RT");
- }
+ iwl_fw_umac_set_alive_err_table(mvm->trans,
+ umac_error_table);
}
alive_data->valid = status == IWL_ALIVE_STATUS_OK;