drm/amd/pm: Delete vddc_dep_on_dal_pwrl

It was not used by anything anymore.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
index 59af3314ffc40e4fc07e9e8122aeaf36482c6657..bfd8fbb0b49dd0ab3df1e2c0853cd3e2a41215c0 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
@@ -1319,7 +1319,6 @@ static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
        hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
        hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
        hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
-       hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
        hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
        hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
        hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index e02a50f208df3b666501c1c60fbc3e35d5defaf3..15456c1c3614d9a66987719eb9b81c5cb1811a19 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -127,41 +127,6 @@ static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
-static int smu10_init_dynamic_state_adjustment_rule_settings(
-                                                       struct pp_hwmgr *hwmgr)
-{
-       int count = 8;
-       struct phm_clock_voltage_dependency_table *table_clk_vlt;
-
-       table_clk_vlt = kzalloc_flex(*table_clk_vlt, entries, count);
-
-       if (NULL == table_clk_vlt) {
-               pr_err("Can not allocate memory!\n");
-               return -ENOMEM;
-       }
-
-       table_clk_vlt->count = count;
-       table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
-       table_clk_vlt->entries[0].v = 0;
-       table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
-       table_clk_vlt->entries[1].v = 1;
-       table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
-       table_clk_vlt->entries[2].v = 2;
-       table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
-       table_clk_vlt->entries[3].v = 3;
-       table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
-       table_clk_vlt->entries[4].v = 4;
-       table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
-       table_clk_vlt->entries[5].v = 5;
-       table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
-       table_clk_vlt->entries[6].v = 6;
-       table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
-       table_clk_vlt->entries[7].v = 7;
-       hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-
-       return 0;
-}
-
 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
 {
        struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
@@ -175,8 +140,6 @@ static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
        smu10_construct_max_power_limits_table (hwmgr,
                                    &hwmgr->dyn_state.max_clock_voltage_on_ac);
 
-       smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
-
        return 0;
 }
 
@@ -611,9 +574,6 @@ static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
        kfree(pinfo->vdd_dep_on_phyclk);
        pinfo->vdd_dep_on_phyclk = NULL;
 
-       kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-       hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-
        kfree(hwmgr->backend);
        hwmgr->backend = NULL;
 

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
index 7034041cef73ceda26d8080a1a1f9026b44db31d..8f82d7c07e8c8277552d17fd9f59b19ab5a8b3f1 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
@@ -270,41 +270,6 @@ static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
-static int smu8_init_dynamic_state_adjustment_rule_settings(
-                       struct pp_hwmgr *hwmgr,
-                       ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
-{
-       struct phm_clock_voltage_dependency_table *table_clk_vlt;
-
-       table_clk_vlt = kzalloc_flex(*table_clk_vlt, entries, 8);
-
-       if (NULL == table_clk_vlt) {
-               pr_err("Can not allocate memory!\n");
-               return -ENOMEM;
-       }
-
-       table_clk_vlt->count = 8;
-       table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
-       table_clk_vlt->entries[0].v = 0;
-       table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
-       table_clk_vlt->entries[1].v = 1;
-       table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
-       table_clk_vlt->entries[2].v = 2;
-       table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
-       table_clk_vlt->entries[3].v = 3;
-       table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
-       table_clk_vlt->entries[4].v = 4;
-       table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
-       table_clk_vlt->entries[5].v = 5;
-       table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
-       table_clk_vlt->entries[6].v = 6;
-       table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
-       table_clk_vlt->entries[7].v = 7;
-       hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
-
-       return 0;
-}
-
 static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
 {
        struct smu8_hwmgr *data = hwmgr->backend;
@@ -403,9 +368,6 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
        smu8_construct_max_power_limits_table (hwmgr,
                                    &hwmgr->dyn_state.max_clock_voltage_on_ac);
 
-       smu8_init_dynamic_state_adjustment_rule_settings(hwmgr,
-                                   &info->sDISPCLK_Voltage[0]);
-
        return result;
 }
 
@@ -1149,9 +1111,6 @@ static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 {
        if (hwmgr != NULL) {
-               kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-               hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-
                kfree(hwmgr->backend);
                hwmgr->backend = NULL;
        }

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 243a7a12a240fd6f53e4c89a5f541167f06d4715..4b92b52aba2b8298f26f638596dbcfbf221f4e7c 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -814,9 +814,6 @@ static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 
 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 {
-       kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-       hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-
        kfree(hwmgr->backend);
        hwmgr->backend = NULL;
 

diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
index 3ae45eac0c5ca62073f1c9f7b67a32ac4dc4fd2a..1ee7e3044272d47e99de74cee5a7add0032eab84 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
@@ -540,7 +540,6 @@ struct phm_ppt_v1_information {
        struct phm_clock_array *valid_dcefclk_values;
        struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
        struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
-       struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
        struct phm_ppm_table *ppm_parameter_table;
        struct phm_cac_tdp_table *cac_dtp_table;
        struct phm_tdp_table *tdp_table;
@@ -632,7 +631,6 @@ struct phm_dynamic_state_info {
        struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
        struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
        struct phm_clock_voltage_dependency_table *vddc_dependency_on_display_clock;
-       struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
        struct phm_clock_array                    *valid_sclk_values;
        struct phm_clock_array                    *valid_mclk_values;
        struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;