arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC

Add UFS host controller and PHY nodes for SM8750 SoC.

Co-developed-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250327-sm8750_ufs_master-v3-2-bad1f5398d0a@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 5babe6629ce7408a6556ba652fcc9aafcc82f274..4643705021c6ca095a16d8d7cc3adac920b21e82 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
 #include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -3303,6 +3304,108 @@
                        };
                };
 
+               ufs_mem_phy: phy@1d80000 {
+                       compatible = "qcom,sm8750-qmp-ufs-phy";
+                       reg = <0x0 0x01d80000 0x0 0x2000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+                                <&tcsrcc TCSR_UFS_CLKREF_EN>;
+
+                       clock-names = "ref",
+                                     "ref_aux",
+                                     "qref";
+
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
+
+                       power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+                       #clock-cells = <1>;
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               ufs_mem_hc: ufs@1d84000 {
+                       compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+                       reg = <0x0 0x01d84000 0x0 0x3000>;
+
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>,
+                                <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                                <&rpmhcc RPMH_LN_BB_CLK3>,
+                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+                       clock-names = "core_clk",
+                                     "bus_aggr_clk",
+                                     "iface_clk",
+                                     "core_clk_unipro",
+                                     "ref_clk",
+                                     "tx_lane0_sync_clk",
+                                     "rx_lane0_sync_clk",
+                                     "rx_lane1_sync_clk";
+
+                       operating-points-v2 = <&ufs_opp_table>;
+
+                       resets = <&gcc GCC_UFS_PHY_BCR>;
+                       reset-names = "rst";
+
+                       interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "ufs-ddr",
+                                            "cpu-ufs";
+
+                       power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       iommus = <&apps_smmu 0x60 0>;
+                       dma-coherent;
+
+                       lanes-per-direction = <2>;
+
+                       phys = <&ufs_mem_phy>;
+                       phy-names = "ufsphy";
+
+                       #reset-cells = <1>;
+
+                       status = "disabled";
+
+                       ufs_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-100000000 {
+                                       opp-hz = /bits/ 64 <100000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <100000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-403000000 {
+                                       opp-hz = /bits/ 64 <403000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <403000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                               };
+                       };
+               };
+
                apps_rsc: rsc@16500000 {
                        compatible = "qcom,rpmh-rsc";
                        reg = <0x0 0x16500000 0x0 0x10000>,