soc: mediatek: mt8365-mmsys: Fix routing table masks and values

The mmsys driver reads the routing table and writes to the
hardware `val & mask`, but multiple entries in the mmsys
routing table for the MT8365 SoC are setting a 0x0 mask:
this effectively writes .. nothing .. to the hardware.

That would never work, and if the display controller was
actually working with the mmsys doing no routing at all,
that was only because the bootloader was correctly setting
the display controller routing registers before booting the
kernel, and the mmsys was never reset.

Make this table to actually set the routing by adding the
correct register masks to it.

While at it, also change MOUT val definitions to BIT(x), as
the MOUT registers are effectively checking for each bit to
enable output to the corresponding HW.
Please note that, for this SoC, only the MOUT registers are
checking bits (as those can enable multiple outputs), while
the others are purely reading a number to select an input.

Fixes: bc3fc5c05100 ("soc: mediatek: mmsys: add MT8365 support")
Link: https://lore.kernel.org/r/20250212100012.33001-7-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 7abaf048d91e869b25b9cf6a538d2a88bb2de90c..ae37945e6c67ccf87ef1ec9840dfbf5c6759a0f2 100644 (file)
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -14,8 +14,9 @@
 #define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN                0xfd8
 #define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00    0xfdc
 
+#define MT8365_DISP_MS_IN_OUT_MASK                     GENMASK(3, 0)
 #define MT8365_RDMA0_SOUT_COLOR0                       0x1
-#define MT8365_DITHER_MOUT_EN_DSI0                     0x1
+#define MT8365_DITHER_MOUT_EN_DSI0                     BIT(0)
 #define MT8365_DSI0_SEL_IN_DITHER                      0x1
 #define MT8365_RDMA0_SEL_IN_OVL0                       0x0
 #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0                 0x0
@@ -30,52 +31,43 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
        {
                DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
                MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
-               MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL
+       }, {
                DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
                MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
-               MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0
+       }, {
                DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
                MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
-               MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0
+       }, {
                DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
                MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
-               MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0
+       }, {
                DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
                MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
-               MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0
+       }, {
                DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
                MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
-               MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER
+       }, {
                DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
                MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
-               MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
+       }, {
                DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
                MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
                MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
-       },
-       {
+       }, {
                DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
                MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
-               MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1
-       },
-       {
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1
+       }, {
                DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
                MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
-               MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0
+               MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0
        },
 };