drm/msm: Fix a7xx per pipe register programming

GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe
but it needs to be programmed for both.

Program both pipes in hw_init and introducea separate reglist for it in
order to add this register to the dynamic reglist which supports
restoring registers per pipe.

Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info")
Cc: stable@vger.kernel.org
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/691553/
Message-ID: <20251201-gras_nc_mode_fix-v3-1-92a8a10d91d0@gmail.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index b731491dc5225413ae7209ca82576c8fcea2ca7c..ac9a95aab2fb56e1b13f251b0f6fd94de0b018b4 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
        REG_A6XX_UCHE_MODE_CNTL,
        REG_A6XX_RB_NC_MODE_CNTL,
        REG_A6XX_RB_CMP_DBG_ECO_CNTL,
-       REG_A7XX_GRAS_NC_MODE_CNTL,
        REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
        REG_A6XX_UCHE_GBIF_GX_CONFIG,
        REG_A6XX_UCHE_CLIENT_PF,
@@ -1449,6 +1448,12 @@ static const u32 a750_ifpc_reglist_regs[] = {
 
 DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
 
+static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] = {
+       { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+};
+
+DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist);
+
 static const struct adreno_info a7xx_gpus[] = {
        {
                .chip_ids = ADRENO_CHIP_IDS(0x07000200),
@@ -1492,6 +1497,7 @@ static const struct adreno_info a7xx_gpus[] = {
                        .hwcg = a730_hwcg,
                        .protect = &a730_protect,
                        .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
                        .gbif_cx = a640_gbif,
                        .gmu_cgc_mode = 0x00020000,
                },
@@ -1514,6 +1520,7 @@ static const struct adreno_info a7xx_gpus[] = {
                        .hwcg = a740_hwcg,
                        .protect = &a730_protect,
                        .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
                        .gbif_cx = a640_gbif,
                        .gmu_chipid = 0x7020100,
                        .gmu_cgc_mode = 0x00020202,
@@ -1548,6 +1555,7 @@ static const struct adreno_info a7xx_gpus[] = {
                        .hwcg = a740_hwcg,
                        .protect = &a730_protect,
                        .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
                        .ifpc_reglist = &a750_ifpc_reglist,
                        .gbif_cx = a640_gbif,
                        .gmu_chipid = 0x7050001,
@@ -1590,6 +1598,7 @@ static const struct adreno_info a7xx_gpus[] = {
                .a6xx = &(const struct a6xx_info) {
                        .protect = &a730_protect,
                        .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
                        .ifpc_reglist = &a750_ifpc_reglist,
                        .gbif_cx = a640_gbif,
                        .gmu_chipid = 0x7090100,
@@ -1624,6 +1633,7 @@ static const struct adreno_info a7xx_gpus[] = {
                        .hwcg = a740_hwcg,
                        .protect = &a730_protect,
                        .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
                        .gbif_cx = a640_gbif,
                        .gmu_chipid = 0x70f0000,
                        .gmu_cgc_mode = 0x00020222,

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 7e71f6bb5283b9db4490144bee2f4baf0fde3051..2129d230a92b441bfaa7dcd1c3c98910d10993dc 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
                  min_acc_len_64b << 3 |
                  hbb_lo << 1 | ubwc_mode);
 
-       if (adreno_is_a7xx(adreno_gpu))
-               gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
-                         FIELD_PREP(GENMASK(8, 5), hbb_lo));
+       if (adreno_is_a7xx(adreno_gpu)) {
+               for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {
+                       gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
+                                 A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));
+                       gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
+                                 FIELD_PREP(GENMASK(8, 5), hbb_lo));
+               }
+               gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
+                         A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE));
+       }
 
        gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
                  min_acc_len_64b << 23 | hbb_lo << 21);
@@ -865,9 +872,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
        struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
        const struct adreno_reglist_list *reglist;
+       const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;
        void *ptr = a6xx_gpu->pwrup_reglist_ptr;
        struct cpu_gpu_lock *lock = ptr;
        u32 *dest = (u32 *)&lock->regs[0];
+       u32 dyn_pwrup_reglist_count = 0;
        int i;
 
        lock->gpu_req = lock->cpu_req = lock->turn = 0;
@@ -909,7 +918,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
         * (<aperture, shifted 12 bits> <address> <data>), and the length is
         * stored as number for triplets in dynamic_list_len.
         */
-       lock->dynamic_list_len = 0;
+       dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist;
+       if (dyn_pwrup_reglist) {
+               for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {
+                       gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
+                                 A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));
+                       for (i = 0; i < dyn_pwrup_reglist->count; i++) {
+                               if ((dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)) == 0)
+                                       continue;
+                               *dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id);
+                               *dest++ = dyn_pwrup_reglist->regs[i].offset;
+                               *dest++ = gpu_read(gpu, dyn_pwrup_reglist->regs[i].offset);
+                               dyn_pwrup_reglist_count++;
+                       }
+               }
+               gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
+                         A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE));
+       }
+       lock->dynamic_list_len = dyn_pwrup_reglist_count;
 }
 
 static int a7xx_preempt_start(struct msm_gpu *gpu)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 6820216ec5fc9410453eba450b80acda1fdadc0e..4eaa0471124606be93d2dd848fd8208c7eb55e02 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -45,6 +45,7 @@ struct a6xx_info {
        const struct adreno_reglist *hwcg;
        const struct adreno_protect *protect;
        const struct adreno_reglist_list *pwrup_reglist;
+       const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;
        const struct adreno_reglist_list *ifpc_reglist;
        const struct adreno_reglist *gbif_cx;
        const struct adreno_reglist_pipe *nonctxt_reglist;

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 0f8d3de97636c50a0bc4a32a7d0b3ad106b48523..1d0145f8b3ecbd33993553ea97ca95cd07ff9c63 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -188,6 +188,19 @@ static const struct adreno_reglist_list name = {           \
        .count = ARRAY_SIZE(name ## _regs),             \
 };
 
+struct adreno_reglist_pipe_list {
+       /** @reg: List of register **/
+       const struct adreno_reglist_pipe *regs;
+       /** @count: Number of registers in the list **/
+       u32 count;
+};
+
+#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \
+static const struct adreno_reglist_pipe_list name = {          \
+       .regs = name ## _regs,                          \
+       .count = ARRAY_SIZE(name ## _regs),             \
+};
+
 struct adreno_gpu {
        struct msm_gpu base;
        const struct adreno_info *info;