]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: add chip_ops::chan_to_rf18_val to get code of RF register value
authorKuan-Chung Chen <damon.chen@realtek.com>
Fri, 6 Jun 2025 02:04:08 +0000 (10:04 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Tue, 10 Jun 2025 02:06:36 +0000 (10:06 +0800)
The RF 0x18 register stores radio frequency domain parameters, including
band, center channel and bandwidth. This information is used in RF
domain. Add a chip_ops to retrieve the RF 0x18 value, which allows
driver to query for a specific channel.

No logic is changed.

Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20250606020408.17035-1-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/rtw8851b.c
drivers/net/wireless/realtek/rtw89/rtw8852a.c
drivers/net/wireless/realtek/rtw89/rtw8852b.c
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
drivers/net/wireless/realtek/rtw89/rtw8852c.c
drivers/net/wireless/realtek/rtw89/rtw8922a.c
drivers/net/wireless/realtek/rtw89/rtw8922a_rfk.c

index c79164757bd9732bba2c6a8b7dbe7da2e0fe4d56..c93d3ea2b0a41314087c5e187815ef3d9c146901 100644 (file)
@@ -3646,6 +3646,8 @@ struct rtw89_chip_ops {
                               enum rtw89_phy_idx phy_idx);
        int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
        u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
+       u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev,
+                               const struct rtw89_chan *chan);
        void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
                               enum rtw89_phy_idx phy_idx);
        void (*query_ppdu)(struct rtw89_dev *rtwdev,
@@ -6882,6 +6884,17 @@ static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
        return chip->ops->get_thermal(rtwdev, rf_path);
 }
 
+static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev,
+                                             const struct rtw89_chan *chan)
+{
+       const struct rtw89_chip_info *chip = rtwdev->chip;
+
+       if (!chip->ops->chan_to_rf18_val)
+               return 0;
+
+       return chip->ops->chan_to_rf18_val(rtwdev, chan);
+}
+
 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
                                         struct rtw89_rx_phy_ppdu *phy_ppdu,
                                         struct ieee80211_rx_status *status)
index fafa200a9c8debdc86d4b3bbcd53ec8193239160..39df1a255095e00cef55f6500ca07b27717a23fa 100644 (file)
@@ -2402,6 +2402,7 @@ static const struct rtw89_chip_ops rtw8851b_chip_ops = {
        .set_txpwr_ctrl         = rtw8851b_set_txpwr_ctrl,
        .init_txpwr_unit        = rtw8851b_init_txpwr_unit,
        .get_thermal            = rtw8851b_get_thermal,
+       .chan_to_rf18_val       = NULL,
        .ctrl_btg_bt_rx         = rtw8851b_ctrl_btg_bt_rx,
        .query_ppdu             = rtw8851b_query_ppdu,
        .convert_rpl_to_rssi    = NULL,
index cd5987fc52d7dfda938dad59a5b1dc01fb9eef94..dc4eab2e791995669a59aaee5e5a86dc4379bac8 100644 (file)
@@ -2128,6 +2128,7 @@ static const struct rtw89_chip_ops rtw8852a_chip_ops = {
        .set_txpwr_ctrl         = rtw8852a_set_txpwr_ctrl,
        .init_txpwr_unit        = rtw8852a_init_txpwr_unit,
        .get_thermal            = rtw8852a_get_thermal,
+       .chan_to_rf18_val       = NULL,
        .ctrl_btg_bt_rx         = rtw8852a_ctrl_btg_bt_rx,
        .query_ppdu             = rtw8852a_query_ppdu,
        .convert_rpl_to_rssi    = NULL,
index dacdb384de2cf1f028912ccf2d9fab991d7df1aa..1f1e10f2b39d7e4ff556aada1a5878bbc424ffa0 100644 (file)
@@ -755,6 +755,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
        .set_txpwr_ctrl         = rtw8852bx_set_txpwr_ctrl,
        .init_txpwr_unit        = rtw8852bx_init_txpwr_unit,
        .get_thermal            = rtw8852bx_get_thermal,
+       .chan_to_rf18_val       = NULL,
        .ctrl_btg_bt_rx         = rtw8852bx_ctrl_btg_bt_rx,
        .query_ppdu             = rtw8852bx_query_ppdu,
        .convert_rpl_to_rssi    = rtw8852bx_convert_rpl_to_rssi,
index 289dce688d72082f6164ffcdc8c6d9b41bcc253d..4c34f50379087809a9b9c1e34cf89bfa89a53bbb 100644 (file)
@@ -689,6 +689,7 @@ static const struct rtw89_chip_ops rtw8852bt_chip_ops = {
        .set_txpwr_ctrl         = rtw8852bx_set_txpwr_ctrl,
        .init_txpwr_unit        = rtw8852bx_init_txpwr_unit,
        .get_thermal            = rtw8852bx_get_thermal,
+       .chan_to_rf18_val       = NULL,
        .ctrl_btg_bt_rx         = rtw8852bx_ctrl_btg_bt_rx,
        .query_ppdu             = rtw8852bx_query_ppdu,
        .convert_rpl_to_rssi    = rtw8852bx_convert_rpl_to_rssi,
index 2a6143a8d256b025bcc9777d92e147f0bf246379..b39add1b798c0f5cc9926ef1cdc83f216840ab6c 100644 (file)
@@ -2948,6 +2948,7 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
        .set_txpwr_ctrl         = rtw8852c_set_txpwr_ctrl,
        .init_txpwr_unit        = rtw8852c_init_txpwr_unit,
        .get_thermal            = rtw8852c_get_thermal,
+       .chan_to_rf18_val       = NULL,
        .ctrl_btg_bt_rx         = rtw8852c_ctrl_btg_bt_rx,
        .query_ppdu             = rtw8852c_query_ppdu,
        .convert_rpl_to_rssi    = NULL,
index 680168f3146661d36b08bd6a1c16843f576fa844..ca32ccb001074e568691c8ea7af3c6a0a2f7365a 100644 (file)
@@ -2390,6 +2390,48 @@ static u8 rtw8922a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p
        return clamp_t(int, th, 0, U8_MAX);
 }
 
+static u32 rtw8922a_chan_to_rf18_val(struct rtw89_dev *rtwdev,
+                                    const struct rtw89_chan *chan)
+{
+       u32 val = u32_encode_bits(chan->channel, RR_CFGCH_CH);
+
+       switch (chan->band_type) {
+       case RTW89_BAND_2G:
+       default:
+               break;
+       case RTW89_BAND_5G:
+               val |= u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
+                      u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
+               break;
+       case RTW89_BAND_6G:
+               val |= u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
+                      u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
+               break;
+       }
+
+       switch (chan->band_width) {
+       case RTW89_CHANNEL_WIDTH_5:
+       case RTW89_CHANNEL_WIDTH_10:
+       case RTW89_CHANNEL_WIDTH_20:
+       default:
+               break;
+       case RTW89_CHANNEL_WIDTH_40:
+               val |= u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
+               break;
+       case RTW89_CHANNEL_WIDTH_80:
+               val |= u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
+               break;
+       case RTW89_CHANNEL_WIDTH_160:
+               val |= u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
+               break;
+       case RTW89_CHANNEL_WIDTH_320:
+               val |= u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
+               break;
+       }
+
+       return val;
+}
+
 static void rtw8922a_btc_set_rfe(struct rtw89_dev *rtwdev)
 {
        union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
@@ -2761,6 +2803,7 @@ static const struct rtw89_chip_ops rtw8922a_chip_ops = {
        .set_txpwr_ctrl         = rtw8922a_set_txpwr_ctrl,
        .init_txpwr_unit        = NULL,
        .get_thermal            = rtw8922a_get_thermal,
+       .chan_to_rf18_val       = rtw8922a_chan_to_rf18_val,
        .ctrl_btg_bt_rx         = rtw8922a_ctrl_btg_bt_rx,
        .query_ppdu             = rtw8922a_query_ppdu,
        .convert_rpl_to_rssi    = rtw8922a_convert_rpl_to_rssi,
index 1659ea64ade1194e935f9cc0c63daa72338bd84d..fce094c7ce939ee65caeae1aaaa02cbe47b86983 100644 (file)
@@ -36,8 +36,7 @@ void rtw8922a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx)
 
 static
 void rtw8922a_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
-                            u8 central_ch, enum rtw89_band band,
-                            enum rtw89_bandwidth bw)
+                            const struct rtw89_chan *chan)
 {
        const u32 rf_addr[2] = {RR_CFGCH, RR_CFGCH_V1};
        struct rtw89_hal *hal = &rtwdev->hal;
@@ -73,49 +72,9 @@ void rtw8922a_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
                                return;
                        }
 
-                       rf_reg[path][i] &= ~(RR_CFGCH_BAND1 | RR_CFGCH_BW |
+                       rf_reg[path][i] &= ~(RR_CFGCH_BAND1 | RR_CFGCH_BW_V2 |
                                             RR_CFGCH_BAND0 | RR_CFGCH_CH);
-                       rf_reg[path][i] |= u32_encode_bits(central_ch, RR_CFGCH_CH);
-
-                       switch (band) {
-                       case RTW89_BAND_2G:
-                       default:
-                               break;
-                       case RTW89_BAND_5G:
-                               rf_reg[path][i] |=
-                                       u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
-                                       u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
-                               break;
-                       case RTW89_BAND_6G:
-                               rf_reg[path][i] |=
-                                       u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
-                                       u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
-                               break;
-                       }
-
-                       switch (bw) {
-                       case RTW89_CHANNEL_WIDTH_5:
-                       case RTW89_CHANNEL_WIDTH_10:
-                       case RTW89_CHANNEL_WIDTH_20:
-                       default:
-                               break;
-                       case RTW89_CHANNEL_WIDTH_40:
-                               rf_reg[path][i] |=
-                                       u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
-                               break;
-                       case RTW89_CHANNEL_WIDTH_80:
-                               rf_reg[path][i] |=
-                                       u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
-                               break;
-                       case RTW89_CHANNEL_WIDTH_160:
-                               rf_reg[path][i] |=
-                                       u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
-                               break;
-                       case RTW89_CHANNEL_WIDTH_320:
-                               rf_reg[path][i] |=
-                                       u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
-                               break;
-                       }
+                       rf_reg[path][i] |= rtw89_chip_chan_to_rf18_val(rtwdev, chan);
 
                        rtw89_write_rf(rtwdev, path, rf_addr[i],
                                       RFREG_MASK, rf_reg[path][i]);
@@ -126,7 +85,7 @@ void rtw8922a_ctl_band_ch_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
        if (hal->cv != CHIP_CAV)
                return;
 
-       if (band == RTW89_BAND_2G) {
+       if (chan->band_type == RTW89_BAND_2G) {
                rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000);
                rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x00003);
                rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c990);
@@ -145,8 +104,7 @@ void rtw8922a_set_channel_rf(struct rtw89_dev *rtwdev,
                             const struct rtw89_chan *chan,
                             enum rtw89_phy_idx phy_idx)
 {
-       rtw8922a_ctl_band_ch_bw(rtwdev, phy_idx, chan->channel, chan->band_type,
-                               chan->band_width);
+       rtw8922a_ctl_band_ch_bw(rtwdev, phy_idx, chan);
 }
 
 enum _rf_syn_pow {