--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+
+/ {
+ model = "Mbox HSA-500";
+ compatible = "mbox,hsa-500", "qcom,ipq4019";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ ethernet0 = &gmac;
+ led-boot = &led_misc;
+ led-failsafe = &led_misc;
+ led-running = &led_misc;
+ led-upgrade = &led_misc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ soc {
+ counter@4a1000 {
+ compatible = "qcom,qca-gcnt";
+ reg = <0x4a1000 0x4>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 =
+ <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+ };
+
+ reg_pcie_power: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie_power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ enable-active-low;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_lte: lte {
+ label = "blue:lte";
+ gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_wifi: wifi {
+ label = "blue:wifi";
+ gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_misc: misc {
+ label = "green:misc";
+ gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial0_pins: serial0-pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial1_pins: serial1-pinmux {
+ mux {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ pins = "gpio13", "gpio14", "gpio15";
+ function = "blsp_spi0";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ pinmux-cs {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ nand_pins: nand-pins {
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56", "gpio57",
+ "gpio60", "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67", "gpio68",
+ "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
+ };
+
+ sd_pins: sd-pins {
+ data {
+ pins = "gpio23", "gpio24", "gpio25", "gpio26",
+ "gpio28";
+ function = "sdio";
+ drive-strength = <10>;
+ };
+
+ clk {
+ pins = "gpio27";
+ function = "sdio";
+ drive-strength = <16>;
+ };
+ };
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&serial1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x00040000 0x00020000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x00060000 0x00060000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0x000c0000 0x00010000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0x000d0000 0x00010000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "0:APPSBLENV";
+ reg = <0x000e0000 0x00010000>;
+ read-only;
+ };
+
+ partition@f0000 {
+ label = "0:APPSBL";
+ reg = <0x000f0000 0x00080000>;
+ read-only;
+ };
+
+ art: partition@170000 {
+ label = "0:ART";
+ reg = <0x00170000 0x00010000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_art_0: mac-address@0 {
+ reg = <0x0 0x6>;
+ };
+
+ macaddr_art_6: mac-address@6 {
+ reg = <0x6 0x6>;
+ };
+
+ precal_art_1000: precal@1000 {
+ reg = <0x1000 0x2f20>;
+ };
+
+ precal_art_5000: precal@5000 {
+ reg = <0x5000 0x2f20>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&nand {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ nand@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ /*
+ * Do not rename this to "ubi": Qualcomm bootipq
+ * forces ubi.mtd=rootfs on the vendor APPSBL.
+ */
+ label = "rootfs";
+ reg = <0x00000000 0x04000000>;
+ };
+ };
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&cryptobam {
+ num-channels = <4>;
+ qcom,num-ees = <2>;
+ status = "okay";
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ phy-reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&vqmmc {
+ status = "okay";
+};
+
+&sdhci {
+ pinctrl-0 = <&sd_pins>;
+ pinctrl-names = "default";
+ cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <&vqmmc>;
+ status = "okay";
+};
+
+&gmac {
+ status = "okay";
+ nvmem-cells = <&macaddr_art_0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&switch {
+ status = "okay";
+};
+
+&swport1 {
+ label = "lan1";
+ status = "okay";
+};
+
+&swport2 {
+ label = "lan2";
+ status = "okay";
+};
+
+&swport3 {
+ label = "lan3";
+ status = "okay";
+};
+
+&swport4 {
+ label = "lan4";
+ status = "okay";
+};
+
+&swport5 {
+ label = "wan";
+ status = "okay";
+};
+
+&wifi0 {
+ nvmem-cells = <&precal_art_1000>, <&macaddr_art_0>;
+ nvmem-cell-names = "pre-calibration", "mac-address";
+ status = "okay";
+};
+
+&wifi1 {
+ nvmem-cells = <&precal_art_5000>, <&macaddr_art_6>;
+ nvmem-cell-names = "pre-calibration", "mac-address";
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
projects / thirdparty / openwrt.git / commitdiff
