i2c: designware: Disable SMBus interrupts to prevent storms from mis-configured firmware

When probing the I2C master, disable SMBus interrupts to prevent
storms caused by broken firmware mis-configuring IC_SMBUS=1; the
handler never services them and a mis-configured SMBUS Master
extend-clock timeout or SMBUS Slave extend-clock timeout can
flood the CPU.

Signed-off-by: Jinhui Guo <guojinhui.liam@bytedance.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251021075714.3712-2-guojinhui.liam@bytedance.com

diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index d50664377c6b3d5c0ec2e1052abc8811c6ccdbb5..bb5ce0a382f92850e7f2f4c788a022459bc20c71 100644 (file)
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -78,6 +78,7 @@
 #define DW_IC_TX_ABRT_SOURCE                   0x80
 #define DW_IC_ENABLE_STATUS                    0x9c
 #define DW_IC_CLR_RESTART_DET                  0xa8
+#define DW_IC_SMBUS_INTR_MASK                  0xcc
 #define DW_IC_COMP_PARAM_1                     0xf4
 #define DW_IC_COMP_VERSION                     0xf8
 #define DW_IC_SDA_HOLD_MIN_VERS                        0x3131312A /* "111*" == v1.11* */

diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index 41e9b5ecad2013bc8fefdb490ed4f6a3dc513fd0..45bfca05bb300fa81a08520c423febabd75ca2b3 100644 (file)
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -220,6 +220,13 @@ static int i2c_dw_init_master(struct dw_i2c_dev *dev)
        /* Disable the adapter */
        __i2c_dw_disable(dev);
 
+       /*
+        * Mask SMBus interrupts to block storms from broken
+        * firmware that leaves IC_SMBUS=1; the handler never
+        * services them.
+        */
+       regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0);
+
        /* Write standard speed timing parameters */
        regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
        regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);