clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write

[ Upstream commit d1c20885d3b01e6a62e920af4b227abd294d22f3 ]

As per the RZ/G2L HW(Rev.1.30 May2023) manual, there are no "write enable"
bits in the CPG_SIPLL5_CLK1 register.  So fix the CPG_SIPLL5_CLK register
write by removing the "write enable" bits.

Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230518152334.514922-1-biju.das.jz@bp.renesas.com
[geert: Remove CPG_SIPLL5_CLK1_*_WEN bit definitions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 4bf40f6ccd1d1acbcda94ecc7d69accb72f6bb49..22ed543fe6b0663877cb0125dee55b17be16d210 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -603,10 +603,8 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
        }
 
        /* Output clock setting 1 */
-       writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_POSTDIV2_WEN |
-              CPG_SIPLL5_CLK1_REFDIV_WEN  | (params.pl5_postdiv1 << 0) |
-              (params.pl5_postdiv2 << 4) | (params.pl5_refdiv << 8),
-              priv->base + CPG_SIPLL5_CLK1);
+       writel((params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |
+              (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);
 
        /* Output clock setting, SSCG modulation value setting 3 */
        writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index eee780276a9e22005e95674d5679421cf79b09db..6cee9e56acc7220072040aa854d0f2f387aa3011 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -32,9 +32,6 @@
 #define CPG_SIPLL5_STBY_RESETB_WEN     BIT(16)
 #define CPG_SIPLL5_STBY_SSCG_EN_WEN    BIT(18)
 #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20)
-#define CPG_SIPLL5_CLK1_POSTDIV1_WEN   BIT(16)
-#define CPG_SIPLL5_CLK1_POSTDIV2_WEN   BIT(20)
-#define CPG_SIPLL5_CLK1_REFDIV_WEN     BIT(24)
 #define CPG_SIPLL5_CLK4_RESV_LSB       (0xFF)
 #define CPG_SIPLL5_MON_PLL5_LOCK       BIT(4)