clk: renesas: r9a09g056: Add clock and reset entries for RIIC controllers

Add module clock and reset definitions for RIIC controllers 0-8, which
are available on the RZ/V2N (R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index c57583e7f6596ad91bf265a130a3b43633cb3169..a489e718a9c20889b8710a10ae585d23d11081d4 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -154,6 +154,24 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(12, BIT(0))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
+       DEF_MOD("riic_8_ckm",                   CLK_PLLCM33_DIV16, 9, 3, 4, 19,
+                                               BUS_MSTOP(3, BIT(13))),
+       DEF_MOD("riic_0_ckm",                   CLK_PLLCLN_DIV16, 9, 4, 4, 20,
+                                               BUS_MSTOP(1, BIT(1))),
+       DEF_MOD("riic_1_ckm",                   CLK_PLLCLN_DIV16, 9, 5, 4, 21,
+                                               BUS_MSTOP(1, BIT(2))),
+       DEF_MOD("riic_2_ckm",                   CLK_PLLCLN_DIV16, 9, 6, 4, 22,
+                                               BUS_MSTOP(1, BIT(3))),
+       DEF_MOD("riic_3_ckm",                   CLK_PLLCLN_DIV16, 9, 7, 4, 23,
+                                               BUS_MSTOP(1, BIT(4))),
+       DEF_MOD("riic_4_ckm",                   CLK_PLLCLN_DIV16, 9, 8, 4, 24,
+                                               BUS_MSTOP(1, BIT(5))),
+       DEF_MOD("riic_5_ckm",                   CLK_PLLCLN_DIV16, 9, 9, 4, 25,
+                                               BUS_MSTOP(1, BIT(6))),
+       DEF_MOD("riic_6_ckm",                   CLK_PLLCLN_DIV16, 9, 10, 4, 26,
+                                               BUS_MSTOP(1, BIT(7))),
+       DEF_MOD("riic_7_ckm",                   CLK_PLLCLN_DIV16, 9, 11, 4, 27,
+                                               BUS_MSTOP(1, BIT(8))),
        DEF_MOD("sdhi_0_imclk",                 CLK_PLLCLN_DIV8, 10, 3, 5, 3,
                                                BUS_MSTOP(8, BIT(2))),
        DEF_MOD("sdhi_0_imclk2",                CLK_PLLCLN_DIV8, 10, 4, 5, 4,
@@ -217,6 +235,15 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(7, 3, 3, 4),            /* GTM_6_PRESETZ */
        DEF_RST(7, 4, 3, 5),            /* GTM_7_PRESETZ */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
+       DEF_RST(9, 8, 4, 9),            /* RIIC_0_MRST */
+       DEF_RST(9, 9, 4, 10),           /* RIIC_1_MRST */
+       DEF_RST(9, 10, 4, 11),          /* RIIC_2_MRST */
+       DEF_RST(9, 11, 4, 12),          /* RIIC_3_MRST */
+       DEF_RST(9, 12, 4, 13),          /* RIIC_4_MRST */
+       DEF_RST(9, 13, 4, 14),          /* RIIC_5_MRST */
+       DEF_RST(9, 14, 4, 15),          /* RIIC_6_MRST */
+       DEF_RST(9, 15, 4, 16),          /* RIIC_7_MRST */
+       DEF_RST(10, 0, 4, 17),          /* RIIC_8_MRST */
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
        DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */