setup new variable VG_(have_altivec) from auxv::AT_HWCAP

fixed default VSCR in dispatch-ppc32.S (non-java mode = 1)

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@4636

diff --git a/coregrind/m_dispatch/dispatch-ppc32.S b/coregrind/m_dispatch/dispatch-ppc32.S
index cf34a102917df85b72ac89d131266e6f54c1c4fb..5b50f8973ee1a0aa1f793ed1d89ac8ccc21fc973 100644 (file)
--- a/coregrind/m_dispatch/dispatch-ppc32.S
+++ b/coregrind/m_dispatch/dispatch-ppc32.S
@@ -92,9 +92,16 @@ VG_(run_innerloop):
 
        /* set host AltiVec control word to the default mode expected 
           by VEX-generated code. */
-        vsubuwm 3,3,3   /* generate zero */
+        lis     3,VG_(have_altivec)@ha
+        lwz     3,VG_(have_altivec)@l(3)
+        cmplwi  3,0
+        beq     L1
+        /* generate vector {0x0,0x0,0x0,0x00010000} */
+        vspltisw 3,0x1      /* 4x 0x00000001 */
+        vspltisw 4,0x0      /* generate zero */
+        vsldoi  3,4,3,0x6   /* v3 = v3 >> 10 bytes */
         mtvscr  3
-
+L1:
         /* make a stack frame for the code we are calling */
         stwu    1,-16(1)
 

diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index 896aa15cbe951ce9d197d8e011f6485e8799a777..99a0434b6bd56e6db3f837c20a4ad540680b7de5 100644 (file)
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -214,11 +214,13 @@ Bool VG_(thread_stack_next)(ThreadId* tid, Addr* stack_min, Addr* stack_max)
 //////////////////////////////////////////////////////////////////
 // Architecture specifics
 
+#if defined(VGA_ppc32)
 // PPC: what is the cache line size (for dcbz etc) ?  This info is
 // harvested on Linux at startup from the AT_SYSINFO entries.  0 means
 // not-yet-set.
-#if defined(VGA_ppc32)
 Int VG_(cache_line_size_ppc32) = 0;
+// Altivec enabled?  Harvested on startup from the AT_HWCAP entry
+Int VG_(have_altivec) = 0;
 #endif
 
 // X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store

diff --git a/coregrind/m_main.c b/coregrind/m_main.c
index e550457333d348898accb9c126e7f7d194421787..b1c944e85021217d7ff3f96c3e6c6524727f86e4 100644 (file)
--- a/coregrind/m_main.c
+++ b/coregrind/m_main.c
@@ -181,9 +181,10 @@ static int scan_auxv(void* init_sp)
          break;
 
       case AT_HWCAP:
-         VG_(debugLog)(1, "main", "PPC32 hwcaps(1): 0x%x\n", (UInt)auxv->u.a_val);
-         auxv->u.a_val &= ~0x10000000; /* claim there is no Altivec support */
-         VG_(debugLog)(1, "main", "PPC32 hwcaps(2): 0x%x\n", (UInt)auxv->u.a_val);
+         VG_(debugLog)(1, "main", "PPC32 hwcaps: 0x%x\n", (UInt)auxv->u.a_val);
+         if ((auxv->u.a_val & 0x10000000) > 0)
+            VG_(have_altivec) = 1;
+         VG_(debugLog)(1, "main", "PPC32 AltiVec support: %u\n", VG_(have_altivec));
          break;
 #     endif
 

diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c
index 2e0e028bf78d7919215f4da4fa2577d6767e9755..0eb81421af1dbd67c34c144519deb8f166082123 100644 (file)
--- a/coregrind/m_translate.c
+++ b/coregrind/m_translate.c
@@ -34,6 +34,7 @@
 #include "pub_core_aspacemgr.h"
 #include "pub_core_cpuid.h"
 #include "pub_core_machine.h"       // For VG_(cache_line_size_ppc32)
+                                    // and VG_(have_altivec)
                                     // and VG_(get_SP)
                                     // and VG_(have_mxcsr_x86)
 #include "pub_core_libcbase.h"
@@ -112,7 +113,8 @@ static Bool getArchAndArchInfo( /*OUT*/VexArch*     vex_arch,
 
 #elif defined(VGA_ppc32)
    *vex_arch    = VexArchPPC32;
-   vai->subarch = VexSubArchPPC32_noAV;
+   vai->subarch = VG_(have_altivec) ? VexSubArchPPC32_AV
+                                    : VexSubArchPPC32_noAV;
    vai->ppc32_cache_line_szB = VG_(cache_line_size_ppc32);
    return True;
 

diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h
index ed448814dab8176b930a4e282a001470a8b37c75..281d4bda3b10a76b362a42219b6f51a1a623dde8 100644 (file)
--- a/coregrind/pub_core_machine.h
+++ b/coregrind/pub_core_machine.h
@@ -78,11 +78,13 @@
 
 // Architecture specifics
 
+#if defined(VGA_ppc32)
 // PPC: what is the cache line size (for dcbz etc) ?
 // This info is harvested on Linux at startup from the AT_SYSINFO
 // entries.
-#if defined(VGA_ppc32)
 extern Int VG_(cache_line_size_ppc32);
+// Altivec enabled?  Harvested on startup from the AT_HWCAP entry
+extern Int VG_(have_altivec);
 #endif
 
 // X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store