drm/msm/a6xx: Increase pwrup_reglist size

To make room for appending SEL reg programming.  Without increasing the
size, we would overflow the pwrup_reglist at ~190 counters on gen8.
Or possibly fewer, considering that some gen8 counter groups also have
separate slice vs unslice SELectors.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728228/
Message-ID: <20260526145137.160554-15-robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 2178b496097951e59122303976a05cbb69072892..8613d21cecb5f67bd47a6cbb69a1cd5577bbc5b7 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1106,7 +1106,7 @@ static int a6xx_ucode_load(struct msm_gpu *gpu)
                msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow");
        }
 
-       a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE,
+       a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PWRUP_REGLIST_SIZE,
                                                         MSM_BO_WC  | MSM_BO_MAP_PRIV,
                                                         gpu->vm, &a6xx_gpu->pwrup_reglist_bo,
                                                         &a6xx_gpu->pwrup_reglist_iova);

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 3491a24a9320b967b3e3b64c43c7e8501fd29581..d3f0b40787db586edd064a808e654b3d2c2062b3 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -96,6 +96,7 @@ struct a6xx_gpu {
        uint32_t *shadow;
 
        struct drm_gem_object *pwrup_reglist_bo;
+#define PWRUP_REGLIST_SIZE (2 * PAGE_SIZE)
        void *pwrup_reglist_ptr;
        uint64_t pwrup_reglist_iova;
        bool pwrup_reglist_emitted;