drm/i915/wm: Refactor dpkgc value prepration

Refactor the value getting prepped to be written into the PKG_C_LATENCY
register by ORing the REG_FIELD_PREP values instead of having val
getting operated on twice.
We dont need the clear and val variables to be initialized.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241203084706.2126189-2-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index c40e0173a5bd626fcf6ff2bba60764c254f80acf..df961cb8d51fca18c1aa93935e1b3301e9d1e43f 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2858,7 +2858,7 @@ static void
 skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
 {
        u32 max_latency = LNL_PKG_C_LATENCY_MASK;
-       u32 clear = 0, val = 0;
+       u32 clear, val;
        u32 added_wake_time = 0;
 
        if (DISPLAY_VER(i915) < 20)
@@ -2872,9 +2872,9 @@ skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc)
                        i915->display.sagv.block_time_us;
        }
 
-       clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
-       val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
-       val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
+       clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
+       val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
+               REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
 
        intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val);
 }