pwm: pwm-mediatek: Pass PWM_CK_26M_SEL from platform data

In preparation for adding support for new SoCs, remove variable
has_ck_26m_sel from pwm_mediatek_of_data and replace it with a
u16 pwm_ck_26m_sel_reg, meant to hold the register offset for
PWM_CK_26M_SEL.

Also, since the reg offset is guaranteed to never be zero, the
logic to check for "has_ck_26m_sel" is changed to check if the
register offset in pwm_ck_26m_sel_reg is more than zero.

Analogously, when writing, use the register offset from platform
data instead of using the PWM_CK_26M_SEL definition.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250623120118.109170-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 33d3554b9197ab0bc8b99731a1d7be9f69d90f61..680ab2346c7188b5d8baa25832aab7d4e076b50e 100644 (file)
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -36,7 +36,7 @@
 struct pwm_mediatek_of_data {
        unsigned int num_pwms;
        bool pwm45_fixup;
-       bool has_ck_26m_sel;
+       u16 pwm_ck_26m_sel_reg;
        const unsigned int *reg_offset;
 };
 
@@ -136,8 +136,8 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
        }
 
        /* Make sure we use the bus clock and not the 26MHz clock */
-       if (pc->soc->has_ck_26m_sel)
-               writel(0, pc->regs + PWM_CK_26M_SEL);
+       if (pc->soc->pwm_ck_26m_sel_reg)
+               writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
 
        /* Using resolution in picosecond gets accuracy higher */
        resolution = (u64)NSEC_PER_SEC * 1000;
@@ -294,84 +294,78 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
        .num_pwms = 8,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = false,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt6795_pwm_data = {
        .num_pwms = 7,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = false,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
        .num_pwms = 6,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = true,
+       .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
        .num_pwms = 5,
        .pwm45_fixup = true,
-       .has_ck_26m_sel = false,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
        .num_pwms = 4,
        .pwm45_fixup = true,
-       .has_ck_26m_sel = false,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
        .num_pwms = 1,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = false,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt7981_pwm_data = {
        .num_pwms = 3,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = true,
+       .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .reg_offset = mtk_pwm_reg_offset_v2,
 };
 
 static const struct pwm_mediatek_of_data mt7986_pwm_data = {
        .num_pwms = 2,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = true,
+       .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt7988_pwm_data = {
        .num_pwms = 8,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = false,
        .reg_offset = mtk_pwm_reg_offset_v2,
 };
 
 static const struct pwm_mediatek_of_data mt8183_pwm_data = {
        .num_pwms = 4,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = true,
+       .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt8365_pwm_data = {
        .num_pwms = 3,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = true,
+       .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };
 
 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
        .num_pwms = 5,
        .pwm45_fixup = false,
-       .has_ck_26m_sel = true,
+       .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
        .reg_offset = mtk_pwm_reg_offset_v1,
 };