riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader

Add bootph-pre-ram hinting to jh7110-common.dtsi:
  - i2c5_pins and i2c-pins subnode for connection to eeprom
  - eeprom node
  - qspi flash configuration subnode
  - memory node
  - mmc0 for eMMC
  - mmc1 for SD Card
  - uart0 for serial console

  With this the U-Boot SPL secondary program loader may drop such overrides.

Signed-off-by: E Shattow <e@freeshell.de>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index e7286c918c9b3f4079b5ba42063cba6462a49dae..4baeb981d4dfd1ee63ad9f82cd1bae74aa8c931a 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -29,6 +29,7 @@
        memory@40000000 {
                device_type = "memory";
                reg = <0x0 0x40000000 0x1 0x0>;
+               bootph-pre-ram;
        };
 
        gpio-restart {
@@ -250,6 +251,7 @@
        eeprom@50 {
                compatible = "atmel,24c04";
                reg = <0x50>;
+               bootph-pre-ram;
                pagesize = <16>;
        };
 };
@@ -269,6 +271,7 @@
        assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
        assigned-clock-rates = <50000000>;
        bus-width = <8>;
+       bootph-pre-ram;
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
        mmc-hs200-1_8v;
@@ -286,6 +289,7 @@
        assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
        assigned-clock-rates = <50000000>;
        bus-width = <4>;
+       bootph-pre-ram;
        no-sdio;
        no-mmc;
        cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
@@ -324,6 +328,7 @@
        nor_flash: flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0>;
+               bootph-pre-ram;
                cdns,read-delay = <2>;
                spi-max-frequency = <100000000>;
                cdns,tshsl-ns = <1>;
@@ -403,6 +408,8 @@
        };
 
        i2c5_pins: i2c5-0 {
+               bootph-pre-ram;
+
                i2c-pins {
                        pinmux = <GPIOMUX(19, GPOUT_LOW,
                                              GPOEN_SYS_I2C5_CLK,
@@ -411,6 +418,7 @@
                                              GPOEN_SYS_I2C5_DATA,
                                              GPI_SYS_I2C5_DATA)>;
                        bias-disable; /* external pull-up */
+                       bootph-pre-ram;
                        input-enable;
                        input-schmitt-enable;
                };
@@ -639,6 +647,7 @@
 };
 
 &uart0 {
+       bootph-pre-ram;
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_pins>;
        status = "okay";