clk: sunxi: Add support for the A523 -R CCU

Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 74e89b863013aebc6eba5f4ecc6493291ed60a9d..1c1cc82719cd48570ede85b8ab2d832e9761a2b9 100644 (file)
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -136,4 +136,11 @@ config CLK_SUN55I_A523
          This enables common clock driver support for platforms based
          on Allwinner A523/T527 SoC.
 
+config CLK_SUN55I_A523_R
+       bool "Clock driver for Allwinner A523 generation PRCM"
+       default MACH_SUN55I_A523
+       help
+         This enables common clock driver support for the PRCM
+         in Allwinner A523/T527 SoCs.
+
 endif # CLK_SUNXI

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index dd33eabe2edba4d9fa1a3c782a11990f24c8fcfb..93b542cebcdc282ef4e31212ad6a723ed8e19379 100644 (file)
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
 obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o
 obj-$(CONFIG_CLK_SUN55I_A523) += clk_a523.o
+obj-$(CONFIG_CLK_SUN55I_A523_R) += clk_a523_r.o

diff --git a/drivers/clk/sunxi/clk_a523_r.c b/drivers/clk/sunxi/clk_a523_r.c
new file mode 100644 (file)
index 0000000..01e613d
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a523_r.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Arm Ltd.
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
+#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a523_r_gates[] = {
+       [CLK_R_AHB]             = GATE_DUMMY,
+       [CLK_R_APB0]            = GATE_DUMMY,
+       [CLK_R_APB1]            = GATE_DUMMY,
+       [CLK_BUS_R_TWD]         = GATE(0x12c, BIT(0)),
+       [CLK_BUS_R_I2C0]        = GATE(0x19c, BIT(0)),
+       [CLK_BUS_R_I2C1]        = GATE(0x19c, BIT(1)),
+       [CLK_BUS_R_I2C2]        = GATE(0x19c, BIT(2)),
+       [CLK_BUS_R_RTC]         = GATE(0x20c, BIT(0)),
+};
+
+static struct ccu_reset a523_r_resets[] = {
+       [RST_BUS_R_TWD]         = RESET(0x12c, BIT(16)),
+       [RST_BUS_R_UART0]       = RESET(0x18c, BIT(16)),
+       [RST_BUS_R_I2C0]        = RESET(0x19c, BIT(16)),
+       [RST_BUS_R_I2C1]        = RESET(0x19c, BIT(17)),
+       [RST_BUS_R_I2C2]        = RESET(0x19c, BIT(18)),
+       [RST_BUS_R_PPU1]        = RESET(0x1ac, BIT(17)),
+       [RST_BUS_R_RTC]         = RESET(0x20c, BIT(16)),
+};
+
+const struct ccu_desc a523_r_ccu_desc = {
+       .gates = a523_r_gates,
+       .resets = a523_r_resets,
+       .num_gates = ARRAY_SIZE(a523_r_gates),
+       .num_resets = ARRAY_SIZE(a523_r_resets),
+};

diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 30baabaafcd092aa9f4d1d4fcd59da5f21b0cf43..842a0541bd6037749d71bbd9b5ca4251677ec45a 100644 (file)
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -127,6 +127,7 @@ extern const struct ccu_desc h6_r_ccu_desc;
 extern const struct ccu_desc r40_ccu_desc;
 extern const struct ccu_desc v3s_ccu_desc;
 extern const struct ccu_desc a523_ccu_desc;
+extern const struct ccu_desc a523_r_ccu_desc;
 
 static const struct udevice_id sunxi_clk_ids[] = {
 #ifdef CONFIG_CLK_SUN4I_A10
@@ -228,6 +229,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
 #ifdef CONFIG_CLK_SUN55I_A523
        { .compatible = "allwinner,sun55i-a523-ccu",
          .data = (ulong)&a523_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN55I_A523_R
+       { .compatible = "allwinner,sun55i-a523-r-ccu",
+         .data = (ulong)&a523_r_ccu_desc },
 #endif
        { }
 };