arm64: dts: mt8167: Reorder nodes according to mmio address

In preparation for adding display nodes. No other changes.

Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 2374c095305755a2aad6d51a3a173b18109a7a75..27cf32d7ae35f79f81f6fb98f5524c8d05ace1b5 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -29,12 +29,6 @@
                        #clock-cells = <1>;
                };
 
-               apmixedsys: apmixedsys@10018000 {
-                       compatible = "mediatek,mt8167-apmixedsys", "syscon";
-                       reg = <0 0x10018000 0 0x710>;
-                       #clock-cells = <1>;
-               };
-
                scpsys: syscon@10006000 {
                        compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
                        reg = <0 0x10006000 0 0x1000>;
@@ -101,18 +95,6 @@
                        };
                };
 
-               imgsys: syscon@15000000 {
-                       compatible = "mediatek,mt8167-imgsys", "syscon";
-                       reg = <0 0x15000000 0 0x1000>;
-                       #clock-cells = <1>;
-               };
-
-               vdecsys: syscon@16000000 {
-                       compatible = "mediatek,mt8167-vdecsys", "syscon";
-                       reg = <0 0x16000000 0 0x1000>;
-                       #clock-cells = <1>;
-               };
-
                pio: pinctrl@1000b000 {
                        compatible = "mediatek,mt8167-pinctrl";
                        reg = <0 0x1000b000 0 0x1000>;
@@ -124,12 +106,36 @@
                        interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               apmixedsys: apmixedsys@10018000 {
+                       compatible = "mediatek,mt8167-apmixedsys", "syscon";
+                       reg = <0 0x10018000 0 0x710>;
+                       #clock-cells = <1>;
+               };
+
+               iommu: m4u@10203000 {
+                       compatible = "mediatek,mt8167-m4u";
+                       reg = <0 0x10203000 0 0x1000>;
+                       mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
+                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+                       #iommu-cells = <1>;
+               };
+
                mmsys: syscon@14000000 {
                        compatible = "mediatek,mt8167-mmsys", "syscon";
                        reg = <0 0x14000000 0 0x1000>;
                        #clock-cells = <1>;
                };
 
+               larb0: larb@14016000 {
+                       compatible = "mediatek,mt8167-smi-larb";
+                       reg = <0 0x14016000 0 0x1000>;
+                       mediatek,smi = <&smi_common>;
+                       clocks = <&mmsys CLK_MM_SMI_LARB0>,
+                                <&mmsys CLK_MM_SMI_LARB0>;
+                       clock-names = "apb", "smi";
+                       power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+               };
+
                smi_common: smi@14017000 {
                        compatible = "mediatek,mt8167-smi-common";
                        reg = <0 0x14017000 0 0x1000>;
@@ -139,14 +145,10 @@
                        power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
                };
 
-               larb0: larb@14016000 {
-                       compatible = "mediatek,mt8167-smi-larb";
-                       reg = <0 0x14016000 0 0x1000>;
-                       mediatek,smi = <&smi_common>;
-                       clocks = <&mmsys CLK_MM_SMI_LARB0>,
-                                <&mmsys CLK_MM_SMI_LARB0>;
-                       clock-names = "apb", "smi";
-                       power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+               imgsys: syscon@15000000 {
+                       compatible = "mediatek,mt8167-imgsys", "syscon";
+                       reg = <0 0x15000000 0 0x1000>;
+                       #clock-cells = <1>;
                };
 
                larb1: larb@15001000 {
@@ -159,6 +161,12 @@
                        power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
                };
 
+               vdecsys: syscon@16000000 {
+                       compatible = "mediatek,mt8167-vdecsys", "syscon";
+                       reg = <0 0x16000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
                larb2: larb@16010000 {
                        compatible = "mediatek,mt8167-smi-larb";
                        reg = <0 0x16010000 0 0x1000>;
@@ -168,13 +176,5 @@
                        clock-names = "apb", "smi";
                        power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
                };
-
-               iommu: m4u@10203000 {
-                       compatible = "mediatek,mt8167-m4u";
-                       reg = <0 0x10203000 0 0x1000>;
-                       mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
-                       interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
-                       #iommu-cells = <1>;
-               };
        };
 };