case Iop_QNarrowBin16Sto8Ux16:
case Iop_QNarrowBin16Sto8Sx16:
case Iop_QNarrowBin16Uto8Ux16:
+ case Iop_QNarrowBin64Sto32Sx4:
+ case Iop_QNarrowBin64Uto32Ux4:
return Iop_NarrowBin16to8x16;
case Iop_QNarrowBin32Sto16Ux8:
case Iop_QNarrowBin32Sto16Sx8:
IRAtom *at1, *at2, *at3;
IRAtom* (*pcast)( MCEnv*, IRAtom* );
switch (narrow_op) {
+ case Iop_QNarrowBin64Sto32Sx4: pcast = mkPCast32x4; break;
+ case Iop_QNarrowBin64Uto32Ux4: pcast = mkPCast32x4; break;
case Iop_QNarrowBin32Sto16Sx8: pcast = mkPCast32x4; break;
case Iop_QNarrowBin32Uto16Ux8: pcast = mkPCast32x4; break;
case Iop_QNarrowBin32Sto16Ux8: pcast = mkPCast32x4; break;
case Iop_Sar32x4:
case Iop_Sal32x4:
case Iop_Rol32x4:
+ case Iop_Rol64x2:
return mkUifUV128(mce,
assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
mkPCast32x4(mce,vatom2)
case Iop_Sub64x2:
case Iop_Add64x2:
+ case Iop_Max64Sx2:
+ case Iop_Max64Ux2:
+ case Iop_Min64Sx2:
+ case Iop_Min64Ux2:
case Iop_CmpEQ64x2:
case Iop_CmpGT64Sx2:
+ case Iop_CmpGT64Ux2:
case Iop_QSal64x2:
case Iop_QShl64x2:
case Iop_QAdd64Ux2:
case Iop_QSub64Sx2:
return binary64Ix2(mce, vatom1, vatom2);
+ case Iop_QNarrowBin64Sto32Sx4:
+ case Iop_QNarrowBin64Uto32Ux4:
case Iop_QNarrowBin32Sto16Sx8:
case Iop_QNarrowBin32Uto16Ux8:
case Iop_QNarrowBin32Sto16Ux8:
return at;
}
+ /* Same deal as Iop_MullEven16{S,U}x8 */
+ case Iop_MullEven32Ux4:
+ case Iop_MullEven32Sx4: {
+ IRAtom* at;
+ at = binary32Ix4(mce,vatom1,vatom2);
+ at = assignNew('V', mce, Ity_V128, binop(Iop_ShlN64x2, at, mkU8(32)));
+ at = assignNew('V', mce, Ity_V128, binop(Iop_SarN64x2, at, mkU8(32)));
+ return at;
+ }
+
/* narrow 2xV128 into 1xV128, hi half from left arg, in a 2 x
32x4 -> 16x8 laneage, discarding the upper half of each lane.
Simply apply same op to the V bits, since this really no more
{ DEFOP(Iop_MulHi32Sx4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_MullEven8Ux16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_MullEven16Ux8, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_MullEven32Ux4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_MullEven8Sx16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_MullEven16Sx8, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_MullEven32Sx4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Mull8Ux8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Mull8Sx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Mull16Ux4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Max8Sx16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Max16Sx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Max32Sx4, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_Max64Sx2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Max8Ux16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Max16Ux8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Max32Ux4, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_Max64Ux2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Min8Sx16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Min16Sx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Min32Sx4, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_Min64Sx2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Min8Ux16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Min16Ux8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Min32Ux4, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_Min64Ux2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_CmpEQ8x16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_CmpEQ16x8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_CmpEQ32x4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_CmpGT8Ux16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_CmpGT16Ux8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_CmpGT32Ux4, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_CmpGT64Ux2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Cnt8x16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Clz8Sx16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Clz16Sx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Rol8x16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Rol16x8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Rol32x4, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_Rol64x2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QShl8x16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QShl16x8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QShl32x4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn16Sto8Sx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn32Sto16Sx4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn64Sto32Sx2, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_QNarrowBin64Sto32Sx4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn16Sto8Ux8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn32Sto16Ux4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn64Sto32Ux2, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_QNarrowBin64Uto32Ux4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn16Uto8Ux8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn32Uto16Ux4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QNarrowUn64Uto32Ux2, UNDEF_UNKNOWN), },
vaddudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> e3e5e7e9ebedeff0
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f3f5f7f9fdfbfdfe
+vsubudm: 0102030405060708 @@ 0102030405060708, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vsubudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0f0f0f0f0f0f0f10
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0f0f0f0f0f0f0f10
+vsubudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f0f0f0f0f0f0f0f0
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> f0f0f0f0f0f0f0f0
+vsubudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000000
+
+vmaxud: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vmaxud: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vmaxsd: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vmaxsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 090a0b0c0e0d0e0f
+vmaxsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0102030405060708
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vmaxsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vminud: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vminud: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 090a0b0c0e0d0e0f
+vminud: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0102030405060708
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vminud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vminsd: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vminsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vcmpequd: 0102030405060708 @@ 0102030405060708, ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> ffffffffffffffff
+vcmpequd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> ffffffffffffffff
+
+vcmpgtud: 0102030405060708 @@ 0102030405060708, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpgtud: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> ffffffffffffffff
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000000
+
+vcmpgtsd: 0102030405060708 @@ 0102030405060708, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpgtsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> ffffffffffffffff
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000000
+
+vrld: 0102030405060708 @@ 0102030405060708, ==> 0203040506070801
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0586070687078485
+vrld: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0801020304050607
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 8485058607068707
+vrld: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f2f3f4f5f6f7f8f1
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 7dfe7f7eff7ffcfd
+vrld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f8f1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> fcfd7dfe7f7eff7f
+
+vsld: 0102030405060708 @@ 0102030405060708, ==> 0203040506070800
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0586070687078000
+vsld: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0800000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 8000000000000000
+vsld: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f2f3f4f5f6f7f800
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 7dfe7f7eff7f8000
+vsld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f800000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 8000000000000000
+
+vsrad: 0102030405060708 @@ 0102030405060708, ==> 0001020304050607
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000121416181c1a
+vsrad: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000001
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vsrad: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> fff1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> fffff3f5f7f9fdfb
+vsrad: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> fffffffffffffff1
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> ffffffffffffffff
+
+vsrd: 0102030405060708 @@ 0102030405060708, ==> 0001020304050607
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000121416181c1a
+vsrd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000001
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vsrd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 00f1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 0001f3f5f7f9fdfb
+vsrd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 00000000000000f1
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000001
+
vpkudum: Inputs: 05060708 0e0d0e0f 05060708 0e0d0e0f
Output: 05060708 0e0d0e0f 05060708 0e0d0e0f
vpkudum: Inputs: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
vpkudum: Inputs: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
Output: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
-All done. Tested 7 different instructions
+vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
+vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
+vmulouw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
+vmulouw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> ec52a4e230d08040 fdfd020406050201
+
+vmuluwm: 01020304 05060708 090a0b0c 0e0d0e0f ==> 14191810a4917040 b56a0890124ba4e1
+vmuluwm: 01020304 05060708 090a0b0c 0e0d0e0f ==> 7c8fabd0184f87c0 346fa3d0b9c6e2f1
+vmuluwm: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 7c8fabd0184f87c0 346fa3d0b9c6e2f1
+vmuluwm: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 89c9209030d08040 5838201006050201
+
+vmulosw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
+vmulosw: 01020304 05060708 090a0b0c 0e0d0e0f ==> ffcd965b184f87c0 fff1d6c9b9c6e2f1
+vmulosw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> ffcd965b184f87c0 fff1d6c9b9c6e2f1
+vmulosw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 0064b4f230d08040 0001040606050201
+
+vmuleuw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0001040a14191810 0051b52bb56a0890
+vmuleuw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00f3d9b37c8fabd0 08d3a173346fa3d0
+vmuleuw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 00f3d9b37c8fabd0 08d3a173346fa3d0
+vmuleuw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> e4ab55e389c92090 f41a344158382010
+
+vmulesw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0001040a14191810 0051b52bb56a0890
+vmulesw: 01020304 05060708 090a0b0c 0e0d0e0f ==> fff1d6af7c8fabd0 ffc99667346fa3d0
+vmulesw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fff1d6af7c8fabd0 ffc99667346fa3d0
+vmulesw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 00c56dfb89c92090 00243c4958382010
+
+vmrgew: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0102030401020304 090a0b0c090a0b0c
+vmrgew: 01020304 05060708 090a0b0c 0e0d0e0f ==> 01020304f1f2f3f4 090a0b0cf9fafbfc
+vmrgew: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f1f2f3f401020304 f9fafbfc090a0b0c
+vmrgew: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f1f2f3f4f1f2f3f4 f9fafbfcf9fafbfc
+
+vmrgow: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0506070805060708 0e0d0e0f0e0d0e0f
+vmrgow: 01020304 05060708 090a0b0c 0e0d0e0f ==> 05060708f5f6f7f8 0e0d0e0ffefdfeff
+vmrgow: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f5f6f7f805060708 fefdfeff0e0d0e0f
+vmrgow: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f5f6f7f8f5f6f7f8 fefdfefffefdfeff
+
+vpkudus: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b f1112345 7c118a2b f1112345
+vpkudus: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b f1112345 ffffffff ffffffff
+vpkudus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> ffffffff ffffffff 7c118a2b f1112345
+vpkudus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> ffffffff ffffffff ffffffff ffffffff
+
+vpksdus: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b f1112345 7c118a2b f1112345
+vpksdus: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b f1112345 ffffffff 00000000
+vpksdus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> ffffffff 00000000 7c118a2b f1112345
+vpksdus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> ffffffff 00000000 ffffffff 00000000
+
+vpksdss: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b 7fffffff 7c118a2b 7fffffff
+vpksdss: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b 7fffffff 7fffffff 80000000
+vpksdss: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> 7fffffff 80000000 7c118a2b 7fffffff
+vpksdss: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7fffffff 80000000 7fffffff 80000000
+
+vupkhsw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0000000001020304 0000000005060708
+vupkhsw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fffffffff1f2f3f4 fffffffff5f6f7f8
+
+vupklsw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00000000090a0b0c 000000000e0d0e0f
+vupklsw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fffffffff9fafbfc fffffffffefdfeff
+
+All done. Tested 31 different instructions
vaddudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> e3e5e7e9ebedeff0
f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f3f5f7f9fdfbfdfe
+vsubudm: 0102030405060708 @@ 0102030405060708, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vsubudm: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0f0f0f0f0f0f0f10
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0f0f0f0f0f0f0f10
+vsubudm: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f0f0f0f0f0f0f0f0
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> f0f0f0f0f0f0f0f0
+vsubudm: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000000
+
+vmaxud: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vmaxud: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> f9fafbfcfefdfeff
+vmaxud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vmaxsd: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vmaxsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 090a0b0c0e0d0e0f
+vmaxsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0102030405060708
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vmaxsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vminud: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vminud: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 090a0b0c0e0d0e0f
+vminud: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0102030405060708
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vminud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vminsd: 0102030405060708 @@ 0102030405060708, ==> 0102030405060708
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 090a0b0c0e0d0e0f
+vminsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> f9fafbfcfefdfeff
+vminsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f1f2f3f4f5f6f7f8
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> f9fafbfcfefdfeff
+
+vcmpequd: 0102030405060708 @@ 0102030405060708, ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> ffffffffffffffff
+vcmpequd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpequd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> ffffffffffffffff
+
+vcmpgtud: 0102030405060708 @@ 0102030405060708, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpgtud: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> ffffffffffffffff
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> ffffffffffffffff
+vcmpgtud: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000000
+
+vcmpgtsd: 0102030405060708 @@ 0102030405060708, ==> 0000000000000000
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpgtsd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> ffffffffffffffff
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> ffffffffffffffff
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 0000000000000000
+vcmpgtsd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000000
+
+vrld: 0102030405060708 @@ 0102030405060708, ==> 0203040506070801
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0586070687078485
+vrld: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0801020304050607
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 8485058607068707
+vrld: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f2f3f4f5f6f7f8f1
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 7dfe7f7eff7ffcfd
+vrld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f8f1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> fcfd7dfe7f7eff7f
+
+vsld: 0102030405060708 @@ 0102030405060708, ==> 0203040506070800
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0586070687078000
+vsld: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0800000000000000
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 8000000000000000
+vsld: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> f2f3f4f5f6f7f800
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 7dfe7f7eff7f8000
+vsld: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> f800000000000000
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 8000000000000000
+
+vsrad: 0102030405060708 @@ 0102030405060708, ==> 0001020304050607
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000121416181c1a
+vsrad: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000001
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vsrad: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> fff1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> fffff3f5f7f9fdfb
+vsrad: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> fffffffffffffff1
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> ffffffffffffffff
+
+vsrd: 0102030405060708 @@ 0102030405060708, ==> 0001020304050607
+ 090a0b0c0e0d0e0f @@ 090a0b0c0e0d0e0f, ==> 0000121416181c1a
+vsrd: 0102030405060708 @@ f1f2f3f4f5f6f7f8, ==> 0000000000000001
+ 090a0b0c0e0d0e0f @@ f9fafbfcfefdfeff, ==> 0000000000000000
+vsrd: f1f2f3f4f5f6f7f8 @@ 0102030405060708, ==> 00f1f2f3f4f5f6f7
+ f9fafbfcfefdfeff @@ 090a0b0c0e0d0e0f, ==> 0001f3f5f7f9fdfb
+vsrd: f1f2f3f4f5f6f7f8 @@ f1f2f3f4f5f6f7f8, ==> 00000000000000f1
+ f9fafbfcfefdfeff @@ f9fafbfcfefdfeff, ==> 0000000000000001
+
vpkudum: Inputs: 05060708 0e0d0e0f 05060708 0e0d0e0f
Output: 05060708 0e0d0e0f 05060708 0e0d0e0f
vpkudum: Inputs: 05060708 0e0d0e0f f5f6f7f8 fefdfeff
vpkudum: Inputs: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
Output: f5f6f7f8 fefdfeff f5f6f7f8 fefdfeff
-All done. Tested 7 different instructions
+vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
+vmulouw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
+vmulouw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 04d39d63184f87c0 0dfee4d8b9c6e2f1
+vmulouw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> ec52a4e230d08040 fdfd020406050201
+
+vmuluwm: 01020304 05060708 090a0b0c 0e0d0e0f ==> 14191810a4917040 b56a0890124ba4e1
+vmuluwm: 01020304 05060708 090a0b0c 0e0d0e0f ==> 7c8fabd0184f87c0 346fa3d0b9c6e2f1
+vmuluwm: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 7c8fabd0184f87c0 346fa3d0b9c6e2f1
+vmuluwm: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 89c9209030d08040 5838201006050201
+
+vmulosw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00193c6aa4917040 00c56e34124ba4e1
+vmulosw: 01020304 05060708 090a0b0c 0e0d0e0f ==> ffcd965b184f87c0 fff1d6c9b9c6e2f1
+vmulosw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> ffcd965b184f87c0 fff1d6c9b9c6e2f1
+vmulosw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 0064b4f230d08040 0001040606050201
+
+vmuleuw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0001040a14191810 0051b52bb56a0890
+vmuleuw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00f3d9b37c8fabd0 08d3a173346fa3d0
+vmuleuw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 00f3d9b37c8fabd0 08d3a173346fa3d0
+vmuleuw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> e4ab55e389c92090 f41a344158382010
+
+vmulesw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0001040a14191810 0051b52bb56a0890
+vmulesw: 01020304 05060708 090a0b0c 0e0d0e0f ==> fff1d6af7c8fabd0 ffc99667346fa3d0
+vmulesw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fff1d6af7c8fabd0 ffc99667346fa3d0
+vmulesw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> 00c56dfb89c92090 00243c4958382010
+
+vmrgew: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0102030401020304 090a0b0c090a0b0c
+vmrgew: 01020304 05060708 090a0b0c 0e0d0e0f ==> 01020304f1f2f3f4 090a0b0cf9fafbfc
+vmrgew: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f1f2f3f401020304 f9fafbfc090a0b0c
+vmrgew: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f1f2f3f4f1f2f3f4 f9fafbfcf9fafbfc
+
+vmrgow: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0506070805060708 0e0d0e0f0e0d0e0f
+vmrgow: 01020304 05060708 090a0b0c 0e0d0e0f ==> 05060708f5f6f7f8 0e0d0e0ffefdfeff
+vmrgow: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f5f6f7f805060708 fefdfeff0e0d0e0f
+vmrgow: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> f5f6f7f8f5f6f7f8 fefdfefffefdfeff
+
+vpkudus: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b f1112345 7c118a2b f1112345
+vpkudus: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b f1112345 ffffffff ffffffff
+vpkudus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> ffffffff ffffffff 7c118a2b f1112345
+vpkudus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> ffffffff ffffffff ffffffff ffffffff
+
+vpksdus: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b f1112345 7c118a2b f1112345
+vpksdus: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b f1112345 ffffffff 00000000
+vpksdus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> ffffffff 00000000 7c118a2b f1112345
+vpksdus: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> ffffffff 00000000 ffffffff 00000000
+
+vpksdss: 000000007c118a2b, 00000000f1112345 @@ 000000007c118a2b, 00000000f1112345 ==> 7c118a2b 7fffffff 7c118a2b 7fffffff
+vpksdss: 000000007c118a2b, 00000000f1112345 @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7c118a2b 7fffffff 7fffffff 80000000
+vpksdss: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 000000007c118a2b, 00000000f1112345 ==> 7fffffff 80000000 7c118a2b 7fffffff
+vpksdss: 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff @@ 01f2f3f4f5f6f7f8, f9fafbfcfefdfeff ==> 7fffffff 80000000 7fffffff 80000000
+
+vupkhsw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 0000000001020304 0000000005060708
+vupkhsw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fffffffff1f2f3f4 fffffffff5f6f7f8
+
+vupklsw: 01020304 05060708 090a0b0c 0e0d0e0f ==> 00000000090a0b0c 000000000e0d0e0f
+vupklsw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff ==> fffffffff9fafbfc fffffffffefdfeff
+
+All done. Tested 31 different instructions
/* HOW TO COMPILE:
* 32bit build:
- gcc -Winline -Wall -g -O -mregnames -maltivec
+ gcc -Winline -Wall -g -O -mregnames -maltivec -m32
* 64bit build:
gcc -Winline -Wall -g -O -mregnames -maltivec -m64
#define DEFAULT_VSCR 0x0
static vector unsigned long long vec_out, vec_inA, vec_inB;
+static vector unsigned int vec_inA_wd, vec_inB_wd;
/* XXXX these must all be callee-save regs! */
register double f14 __asm__ ("fr14");
PPC_CROP = 0x00000400,
PPC_LDST = 0x00000500,
PPC_POPCNT = 0x00000600,
+ PPC_ARITH_DRES = 0x00000700,
+ PPC_DOUBLE_IN_IRES = 0x00000800,
PPC_MOV = 0x00000A00,
PPC_TYPE = 0x00000F00,
/* Family */
PPC_405 = 0x00030000, // Leave so we keep numbering consistent
PPC_ALTIVEC = 0x00040000,
PPC_FALTIVEC = 0x00050000,
+ PPC_ALTIVECD = 0x00060000, /* double word Altivec tests */
PPC_FAMILY = 0x000F0000,
/* Flags: these may be combined, so use separate bitfields. */
PPC_CR = 0x01000000,
#define AB_DPRINTF(fmt, args...) do { } while (0)
#endif
+
#if defined (DEBUG_FILTER)
#define FDPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
#else
{ NULL, NULL }
};
-/* Vector Double Word tests.
- * NOTE: Since these are "vector" instructions versus VSX, we must use
- * vector constraints. */
+/* NOTE: Since these are "vector" instructions versus VSX, we must use
+ * vector constraints.
+ *
+ * Vector Double Word tests.
+ */
+static void test_vpkudum (void)
+{
+ __asm__ __volatile__ ("vpkudum %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
static void test_vaddudm (void)
{
__asm__ __volatile__ ("vaddudm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
}
-static void test_vpkudum (void)
+static void test_vsubudm (void)
{
- __asm__ __volatile__ ("vpkudum %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+ __asm__ __volatile__ ("vsubudm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vmaxud (void)
+{
+ __asm__ __volatile__ ("vmaxud %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vmaxsd (void)
+{
+ __asm__ __volatile__ ("vmaxsd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vminud (void)
+{
+ __asm__ __volatile__ ("vminud %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vminsd (void)
+{
+ __asm__ __volatile__ ("vminsd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcmpequd (void)
+{
+ __asm__ __volatile__ ("vcmpequd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcmpgtud (void)
+{
+ __asm__ __volatile__ ("vcmpgtud %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vcmpgtsd (void)
+{
+ __asm__ __volatile__ ("vcmpgtsd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vrld (void)
+{
+ __asm__ __volatile__ ("vrld %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsld (void)
+{
+ __asm__ __volatile__ ("vsld %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsrad (void)
+{
+ __asm__ __volatile__ ("vsrad %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vsrd (void)
+{
+ __asm__ __volatile__ ("vsrd %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+/* Vector Double Word saturate tests.*/
+
+static void test_vpkudus (void)
+{
+ __asm__ __volatile__ ("vpkudus %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vpksdus (void)
+{
+ __asm__ __volatile__ ("vpksdus %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+static void test_vpksdss (void)
+{
+ __asm__ __volatile__ ("vpksdss %0, %1, %2" : "=v" (vec_out): "v" (vec_inA),"v" (vec_inB));
+}
+
+
+/* Vector unpack two words from one vector arg */
+static void test_vupkhsw (void)
+{
+ __asm__ __volatile__ ("vupkhsw %0, %1" : "=v" (vec_out): "v" (vec_inB_wd));
+}
+
+static void test_vupklsw (void)
+{
+ __asm__ __volatile__ ("vupklsw %0, %1" : "=v" (vec_out): "v" (vec_inB_wd));
+}
+
+
+/* Vector Integer Word tests.*/
+static void test_vmulouw (void)
+{
+ __asm__ __volatile__ ("vmulouw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmuluwm (void)
+{
+ __asm__ __volatile__ ("vmuluwm %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmulosw (void)
+{
+ __asm__ __volatile__ ("vmulosw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmuleuw (void)
+{
+ __asm__ __volatile__ ("vmuleuw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmulesw (void)
+{
+ __asm__ __volatile__ ("vmulesw %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static void test_vmrgew (void)
+{
+ __asm__ __volatile__ ("vmrgew %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
}
-static test_t tests_aa_dbl_ops_two[] = {
+static void test_vmrgow (void)
+{
+ __asm__ __volatile__ ("vmrgow %0, %1, %2" : "=v" (vec_out): "v" (vec_inA_wd),"v" (vec_inB_wd));
+}
+
+static test_t tests_aa_word_ops_one_arg_dres[] = {
+ { &test_vupkhsw , "vupkhsw" },
+ { &test_vupklsw , "vupklsw" },
+ { NULL , NULL }
+};
+static test_t tests_aa_word_ops_two_args_dres[] = {
+ { &test_vmulouw , "vmulouw" },
+ { &test_vmuluwm , "vmuluwm" },
+ { &test_vmulosw , "vmulosw" },
+ { &test_vmuleuw , "vmuleuw" },
+ { &test_vmulesw , "vmulesw" },
+ { &test_vmrgew , "vmrgew" },
+ { &test_vmrgow , "vmrgow" },
+ { NULL , NULL }
+};
+
+static test_t tests_aa_dbl_ops_two_args[] = {
{ &test_vaddudm , "vaddudm", },
- { &test_vpkudum , "vpkudum", },
- { NULL, NULL, },
+ { &test_vsubudm , "vsubudm", },
+ { &test_vmaxud , "vmaxud", },
+ { &test_vmaxsd , "vmaxsd", },
+ { &test_vminud , "vminud", },
+ { &test_vminsd , "vminsd", },
+ { &test_vcmpequd , "vcmpequd", },
+ { &test_vcmpgtud , "vcmpgtud", },
+ { &test_vcmpgtsd , "vcmpgtsd", },
+ { &test_vrld , "vrld", },
+ { &test_vsld , "vsld", },
+ { &test_vsrad , "vsrad", },
+ { &test_vsrd , "vsrd", },
+ { &test_vpkudum , "vpkudum", },
+ { NULL , NULL, },
+};
+
+static test_t tests_aa_dbl_to_int_two_args[] = {
+ { &test_vpkudus , "vpkudus", },
+ { &test_vpksdus , "vpksdus", },
+ { &test_vpksdss , "vpksdss", },
+ { NULL , NULL, },
};
static int verbose = 0;
static int arg_list_size = 0;
static unsigned long long * vdargs = NULL;
+static unsigned long long * vdargs_x = NULL;
#define NB_VDARGS 4
static void build_vdargs_table (void)
vdargs[1] = 0x090A0B0C0E0D0E0FULL;
vdargs[2] = 0xF1F2F3F4F5F6F7F8ULL;
vdargs[3] = 0xF9FAFBFCFEFDFEFFULL;
+
+ vdargs_x = memalign16(NB_VDARGS * sizeof(unsigned long long));
+ vdargs_x[0] = 0x000000007c118a2bULL;
+ vdargs_x[1] = 0x00000000f1112345ULL;
+ vdargs_x[2] = 0x01F2F3F4F5F6F7F8ULL;
+ vdargs_x[3] = 0xF9FAFBFCFEFDFEFFULL;
+}
+
+static unsigned int * vwargs = NULL;
+#define NB_VWARGS 8
+
+static void build_vwargs_table (void)
+{
+ // Each VSX register holds 4 integer word values
+ size_t i = 0;
+ vwargs = memalign(8, 8 * sizeof(int));
+ assert(vwargs);
+ assert(0 == ((8-1) & (unsigned long)vwargs));
+ vwargs[i++] = 0x01020304;
+ vwargs[i++] = 0x05060708;
+ vwargs[i++] = 0x090A0B0C;
+ vwargs[i++] = 0x0E0D0E0F;
+ vwargs[i++] = 0xF1F2F3F4;
+ vwargs[i++] = 0xF5F6F7F8;
+ vwargs[i++] = 0xF9FAFBFC;
+ vwargs[i++] = 0xFEFDFEFF;
+}
+
+static void build_vargs_table (void)
+{
+ build_vdargs_table();
+ build_vwargs_table();
}
static double *fargs = NULL;
}
}
+/* Vector doubleword-to-int tests, two input args, integer result */
+static void test_av_dint_to_int_two_args (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+
+ unsigned int * dst_int;
+ int i,j;
+ for (i = 0; i < NB_VDARGS; i+=2) {
+ vec_inA = (vector unsigned long long){ vdargs_x[i], vdargs_x[i+1] };
+ for (j = 0; j < NB_VDARGS; j+=2) {
+ vec_inB = (vector unsigned long long){ vdargs_x[j], vdargs_x[j+1] };
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ (*func)();
+ dst_int = (unsigned int *)&vec_out;
+
+ printf("%s: ", name);
+ printf("%016llx, %016llx @@ %016llx, %016llx ",
+ vdargs_x[i], vdargs_x[i+1],
+ vdargs_x[j], vdargs_x[j+1]);
+ printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
+ dst_int[2], dst_int[3]);
+ }
+ }
+}
+
+/* Vector Word tests; two integer args, with double word result */
+
+static void test_av_wint_two_args_dres (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+
+ unsigned long long * dst;
+ int i,j;
+
+ for (i = 0; i < NB_VWARGS; i+=4) {
+ vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
+ for (j = 0; j < NB_VWARGS; j+=4) {
+ vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ (*func)();
+ dst = (unsigned long long *)&vec_out;
+ printf("%s: ", name);
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
+ }
+ }
+}
+
+/* Vector Word tests; one input arg, with double word result */
+
+static void test_av_wint_one_arg_dres (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ unsigned long long * dst;
+ int i;
+ for (i = 0; i < NB_VWARGS; i+=4) {
+ vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ (*func)();
+ dst = (unsigned long long *)&vec_out;
+ printf("%s: ", name);
+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
+ }
+}
+
+
static void test_int_stq_two_regs_imm16 (const char* name,
test_func_t func_IN,
unused uint32_t test_flags)
-/* Used in do_tests */
+/* The ALTIVEC_LOOPS and altive_loops defined below are used in do_tests.
+ * Add new values to the end; do not change order, since the altivec_loops
+ * array is indexed using the enumerated values defined by ALTIVEC_LOOPS.
+ */
enum ALTIVEC_LOOPS {
ALTV_MOV,
- ALTV_INT
+ ALTV_DINT,
+ ALTV_INT_DRES,
+ ALTV_DINT_IRES,
+ ALTV_ONE_INT_DRES
};
+
static test_loop_t altivec_loops[] = {
&test_move_special,
&test_av_dint_two_args,
+ &test_av_wint_two_args_dres,
+ &test_av_dint_to_int_two_args,
+ &test_av_wint_one_arg_dres,
NULL
};
{
tests_move_ops_spe,
"PPC VSR special move insns",
- PPC_ALTIVEC | PPC_MOV | PPC_ONE_ARG,
+ PPC_ALTIVECD | PPC_MOV | PPC_ONE_ARG,
},
{
- tests_aa_dbl_ops_two,
- "PC altivec double word integer insns with two args",
- PPC_ALTIVEC | PPC_ARITH | PPC_TWO_ARGS,
+ tests_aa_dbl_ops_two_args,
+ "PPC altivec double word integer insns (arith, compare) with two args",
+ PPC_ALTIVECD | PPC_ARITH | PPC_TWO_ARGS,
+ },
+ {
+ tests_aa_word_ops_two_args_dres,
+ "PPC altivec integer word instructions with two input args, double word result",
+ PPC_ALTIVEC | PPC_ARITH_DRES | PPC_TWO_ARGS,
+ },
+ {
+ tests_aa_dbl_to_int_two_args,
+ "PPC altivec doubleword-to-integer instructions with two input args, saturated integer result",
+ PPC_ALTIVECD | PPC_DOUBLE_IN_IRES | PPC_TWO_ARGS,
+ },
+ {
+ tests_aa_word_ops_one_arg_dres,
+ "PPC altivec integer word instructions with one input arg, double word result",
+ PPC_ALTIVEC | PPC_ARITH_DRES | PPC_ONE_ARG,
},
{
tests_istq_ops_two_i16,
if ((family == PPC_INTEGER && !seln_flags.integer) ||
(family == PPC_FLOAT && !seln_flags.floats) ||
(family == PPC_ALTIVEC && !seln_flags.altivec) ||
+ (family == PPC_ALTIVECD && !seln_flags.altivec) ||
(family == PPC_FALTIVEC && !seln_flags.faltivec)) {
continue;
}
loop = &float_loops[nb_args - 1];
break;
- case PPC_ALTIVEC:
+ case PPC_ALTIVECD:
switch (type) {
- case PPC_MOV:
- loop = &altivec_loops[ALTV_MOV];
- break;
- case PPC_ARITH:
- loop = &altivec_loops[ALTV_INT];
- break;
- default:
- printf("No altivec test defined for type %x\n", type);
+ case PPC_MOV:
+ loop = &altivec_loops[ALTV_MOV];
+ break;
+ case PPC_ARITH:
+ loop = &altivec_loops[ALTV_DINT];
+ break;
+ case PPC_DOUBLE_IN_IRES:
+ loop = &altivec_loops[ALTV_DINT_IRES];
+ break;
+ default:
+ printf("No altivec test defined for type %x\n", type);
}
break;
printf("Currently there are no floating altivec tests in this testsuite.\n");
break;
+ case PPC_ALTIVEC:
+ switch (type) {
+ case PPC_ARITH_DRES:
+ switch (nb_args) {
+ case 1:
+ loop = &altivec_loops[ALTV_ONE_INT_DRES];
+ break;
+ case 2:
+ loop = &altivec_loops[ALTV_INT_DRES];
+ break;
+ default:
+ printf("No altivec test defined for number args %d\n", nb_args);
+ }
+ break;
+ default:
+ printf("No altivec test defined for type %x\n", type);
+ }
+ break;
+
default:
printf("ERROR: unknown insn family %08x\n", family);
continue;
arg_list_size = 0;
- build_vdargs_table();
+ build_vargs_table();
if (verbose > 1) {
printf("\nInstruction Selection:\n");
printf(" n_args: \n");
projects / thirdparty / valgrind.git / commitdiff
