--- /dev/null
+From 31b153315b8702d0249aa44d83d9fbf42c5c7a79 Mon Sep 17 00:00:00 2001
+From: Perry Yuan <perry.yuan@amd.com>
+Date: Wed, 28 Jan 2026 13:54:31 +0800
+Subject: drm/amdgpu: ensure no_hw_access is visible before MMIO
+
+From: Perry Yuan <perry.yuan@amd.com>
+
+commit 31b153315b8702d0249aa44d83d9fbf42c5c7a79 upstream.
+
+Add a full memory barrier after clearing no_hw_access in
+amdgpu_device_mode1_reset() so subsequent PCI state restore
+access cannot observe stale state on other CPUs.
+
+Fixes: 7edb503fe4b6 ("drm/amd/pm: Disable MMIO access during SMU Mode 1 reset")
+Signed-off-by: Perry Yuan <perry.yuan@amd.com>
+Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: Simon Liebold <simonlie@amazon.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -5743,6 +5743,9 @@ int amdgpu_device_mode1_reset(struct amd
+ /* enable mmio access after mode 1 reset completed */
+ adev->no_hw_access = false;
+
++ /* ensure no_hw_access is updated before we access hw */
++ smp_mb();
++
+ amdgpu_device_load_pci_state(adev->pdev);
+ ret = amdgpu_psp_wait_for_bootloader(adev);
+ if (ret)