]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
media: mali-c55: Initialize the ISP in enable_streams()
authorJacopo Mondi <jacopo.mondi@ideasonboard.com>
Mon, 19 Jan 2026 11:20:56 +0000 (12:20 +0100)
committerHans Verkuil <hverkuil+cisco@kernel.org>
Tue, 24 Mar 2026 15:13:09 +0000 (16:13 +0100)
The Mali C55 driver initializes the ISP in two points:

1) At probe time it disables ISP blocks by configuring them in bypass
   mode
2) At enable_streams() it initializes the crop rectangles and the image
   processing pipeline using the current image format

However, as ISP blocks are configured by userspace, if their
configuration is not reset, from the second enable_streams() call
onwards the ISP configuration will depend on the previous streaming
session configuration.

To re-initialize the ISP completely at enable_streams() time consolidate
the ISP block bypass configuration and the image processing path
configuration in a single function to be called at enabled_streams()
time.

Cc: stable@vger.kernel.org
Fixes: d5f281f3dd29 ("media: mali-c55: Add Mali-C55 ISP driver")
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
drivers/media/platform/arm/mali-c55/mali-c55-common.h
drivers/media/platform/arm/mali-c55/mali-c55-core.c
drivers/media/platform/arm/mali-c55/mali-c55-isp.c
drivers/media/platform/arm/mali-c55/mali-c55-params.c

index 31c1deaca146619870888c31e4f97ca79abe7e04..13a3e9dc424311869af581061190bf38c08fb469 100644 (file)
@@ -306,5 +306,7 @@ bool mali_c55_pipeline_ready(struct mali_c55 *mali_c55);
 void mali_c55_stats_fill_buffer(struct mali_c55 *mali_c55,
                                enum mali_c55_config_spaces cfg_space);
 void mali_c55_params_write_config(struct mali_c55 *mali_c55);
+void mali_c55_params_init_isp_config(struct mali_c55 *mali_c55,
+                                    const struct v4l2_subdev_state *state);
 
 #endif /* _MALI_C55_COMMON_H */
index 43b834459ccf3ef08d8b2007682cf5f4ab2bf1b2..c1a562cd214ec51610ef142b840a99ae91dd4198 100644 (file)
@@ -663,41 +663,6 @@ static int mali_c55_init_context(struct mali_c55 *mali_c55,
                      mali_c55->base + config_space_addrs[MALI_C55_CONFIG_PING],
                      MALI_C55_CONFIG_SPACE_SIZE);
 
-       /*
-        * Some features of the ISP need to be disabled by default and only
-        * enabled at the same time as they're configured by a parameters buffer
-        */
-
-       /* Bypass the sqrt and square compression and expansion modules */
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BYPASS_1,
-                                MALI_C55_REG_BYPASS_1_FE_SQRT,
-                                MALI_C55_REG_BYPASS_1_FE_SQRT);
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BYPASS_3,
-                                MALI_C55_REG_BYPASS_3_SQUARE_BE,
-                                MALI_C55_REG_BYPASS_3_SQUARE_BE);
-
-       /* Bypass the temper module */
-       mali_c55_ctx_write(mali_c55, MALI_C55_REG_BYPASS_2,
-                          MALI_C55_REG_BYPASS_2_TEMPER);
-
-       /* Disable the temper module's DMA read/write */
-       mali_c55_ctx_write(mali_c55, MALI_C55_REG_TEMPER_DMA_IO, 0x0);
-
-       /* Bypass the colour noise reduction  */
-       mali_c55_ctx_write(mali_c55, MALI_C55_REG_BYPASS_4,
-                          MALI_C55_REG_BYPASS_4_CNR);
-
-       /* Disable the sinter module */
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_SINTER_CONFIG,
-                                MALI_C55_SINTER_ENABLE_MASK, 0);
-
-       /* Disable the RGB Gamma module for each output */
-       mali_c55_ctx_write(mali_c55, MALI_C55_REG_FR_GAMMA_RGB_ENABLE, 0);
-       mali_c55_ctx_write(mali_c55, MALI_C55_REG_DS_GAMMA_RGB_ENABLE, 0);
-
-       /* Disable the colour correction matrix */
-       mali_c55_ctx_write(mali_c55, MALI_C55_REG_CCM_ENABLE, 0);
-
        return 0;
 }
 
index 497f25fbdd13b0eb0e3e1b3da924dbbcd291176c..4c0fd1ec741c3b2e0e800d37798cc7649e023523 100644 (file)
@@ -112,9 +112,6 @@ static int mali_c55_isp_start(struct mali_c55 *mali_c55,
                              const struct v4l2_subdev_state *state)
 {
        struct mali_c55_context *ctx = mali_c55_get_active_context(mali_c55);
-       const struct mali_c55_isp_format_info *cfg;
-       const struct v4l2_mbus_framefmt *format;
-       const struct v4l2_rect *crop;
        u32 val;
        int ret;
 
@@ -122,35 +119,11 @@ static int mali_c55_isp_start(struct mali_c55 *mali_c55,
                             MALI_C55_REG_MCU_CONFIG_WRITE_MASK,
                             MALI_C55_REG_MCU_CONFIG_WRITE_PING);
 
-       /* Apply input windowing */
-       crop = v4l2_subdev_state_get_crop(state, MALI_C55_ISP_PAD_SINK_VIDEO);
-       format = v4l2_subdev_state_get_format(state,
-                                             MALI_C55_ISP_PAD_SINK_VIDEO);
-       cfg = mali_c55_isp_get_mbus_config_by_code(format->code);
-
-       mali_c55_write(mali_c55, MALI_C55_REG_HC_START,
-                      MALI_C55_HC_START(crop->left));
-       mali_c55_write(mali_c55, MALI_C55_REG_HC_SIZE,
-                      MALI_C55_HC_SIZE(crop->width));
-       mali_c55_write(mali_c55, MALI_C55_REG_VC_START_SIZE,
-                      MALI_C55_VC_START(crop->top) |
-                      MALI_C55_VC_SIZE(crop->height));
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BASE_ADDR,
-                                MALI_C55_REG_ACTIVE_WIDTH_MASK, format->width);
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BASE_ADDR,
-                                MALI_C55_REG_ACTIVE_HEIGHT_MASK,
-                                format->height << 16);
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BAYER_ORDER,
-                                MALI_C55_BAYER_ORDER_MASK, cfg->order);
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_INPUT_WIDTH,
-                                MALI_C55_INPUT_WIDTH_MASK,
-                                MALI_C55_INPUT_WIDTH_20BIT);
-
-       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_ISP_RAW_BYPASS,
-                                MALI_C55_ISP_RAW_BYPASS_BYPASS_MASK,
-                                cfg->bypass ? MALI_C55_ISP_RAW_BYPASS_BYPASS_MASK :
-                                            0x00);
-
+       /*
+        * Apply default ISP configuration and the apply configurations from
+        * the first available parameters buffer.
+        */
+       mali_c55_params_init_isp_config(mali_c55, state);
        mali_c55_params_write_config(mali_c55);
        ret = mali_c55_config_write(ctx, MALI_C55_CONFIG_PING, true);
        if (ret) {
index c03a6120ddbf41aca3f062c62f4e41b0bc38621e..c84a6047a570fc5c27e4ec425a01649e54d809e3 100644 (file)
@@ -732,6 +732,78 @@ void mali_c55_params_write_config(struct mali_c55 *mali_c55)
        vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
 }
 
+void mali_c55_params_init_isp_config(struct mali_c55 *mali_c55,
+                                    const struct v4l2_subdev_state *state)
+{
+       const struct mali_c55_isp_format_info *cfg;
+       const struct v4l2_mbus_framefmt *format;
+       const struct v4l2_rect *crop;
+
+       /* Apply input windowing */
+       crop = v4l2_subdev_state_get_crop(state, MALI_C55_ISP_PAD_SINK_VIDEO);
+       format = v4l2_subdev_state_get_format(state,
+                                             MALI_C55_ISP_PAD_SINK_VIDEO);
+       cfg = mali_c55_isp_get_mbus_config_by_code(format->code);
+
+       mali_c55_write(mali_c55, MALI_C55_REG_HC_START,
+                      MALI_C55_HC_START(crop->left));
+       mali_c55_write(mali_c55, MALI_C55_REG_HC_SIZE,
+                      MALI_C55_HC_SIZE(crop->width));
+       mali_c55_write(mali_c55, MALI_C55_REG_VC_START_SIZE,
+                      MALI_C55_VC_START(crop->top) |
+                      MALI_C55_VC_SIZE(crop->height));
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BASE_ADDR,
+                                MALI_C55_REG_ACTIVE_WIDTH_MASK, format->width);
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BASE_ADDR,
+                                MALI_C55_REG_ACTIVE_HEIGHT_MASK,
+                                format->height << 16);
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BAYER_ORDER,
+                                MALI_C55_BAYER_ORDER_MASK, cfg->order);
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_INPUT_WIDTH,
+                                MALI_C55_INPUT_WIDTH_MASK,
+                                MALI_C55_INPUT_WIDTH_20BIT);
+
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_ISP_RAW_BYPASS,
+                                MALI_C55_ISP_RAW_BYPASS_BYPASS_MASK,
+                                cfg->bypass ? MALI_C55_ISP_RAW_BYPASS_BYPASS_MASK :
+                                            0x00);
+
+       /*
+        * Some features of the ISP need to be disabled by default and only
+        * enabled at the same time as they're configured by a parameters buffer
+        */
+
+       /* Bypass the sqrt and square compression and expansion modules */
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BYPASS_1,
+                                MALI_C55_REG_BYPASS_1_FE_SQRT,
+                                MALI_C55_REG_BYPASS_1_FE_SQRT);
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_BYPASS_3,
+                                MALI_C55_REG_BYPASS_3_SQUARE_BE,
+                                MALI_C55_REG_BYPASS_3_SQUARE_BE);
+
+       /* Bypass the temper module */
+       mali_c55_ctx_write(mali_c55, MALI_C55_REG_BYPASS_2,
+                          MALI_C55_REG_BYPASS_2_TEMPER);
+
+       /* Disable the temper module's DMA read/write */
+       mali_c55_ctx_write(mali_c55, MALI_C55_REG_TEMPER_DMA_IO, 0x0);
+
+       /* Bypass the colour noise reduction  */
+       mali_c55_ctx_write(mali_c55, MALI_C55_REG_BYPASS_4,
+                          MALI_C55_REG_BYPASS_4_CNR);
+
+       /* Disable the sinter module */
+       mali_c55_ctx_update_bits(mali_c55, MALI_C55_REG_SINTER_CONFIG,
+                                MALI_C55_SINTER_ENABLE_MASK, 0);
+
+       /* Disable the RGB Gamma module for each output */
+       mali_c55_ctx_write(mali_c55, MALI_C55_REG_FR_GAMMA_RGB_ENABLE, 0);
+       mali_c55_ctx_write(mali_c55, MALI_C55_REG_DS_GAMMA_RGB_ENABLE, 0);
+
+       /* Disable the colour correction matrix */
+       mali_c55_ctx_write(mali_c55, MALI_C55_REG_CCM_ENABLE, 0);
+}
+
 void mali_c55_unregister_params(struct mali_c55 *mali_c55)
 {
        struct mali_c55_params *params = &mali_c55->params;