realtek: pcs: Fix overflow in rtpcs_930x_sds_clock_wait

It can happen that the calculation `start + (HZ / 1000) * timeout`
overflows `unsigned long`. This must be handled correctly to avoid too long
waits. Luckily, the `time_before()` helper already does this.

Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/20906
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
index cced6d5168d36b4b67d97d8f2c5fd8c1aba9e0b2..482bc2e08e0a93c57c41ae7ca605ac02202002cd 100644 (file)
--- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
+++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
@@ -685,13 +685,14 @@ static int rtpcs_930x_sds_clock_wait(struct rtpcs_ctrl *ctrl, int timeout)
 {
        u32 v;
        unsigned long start = jiffies;
+       unsigned long end = start + (HZ / 1000) * timeout;
 
        do {
                rtpcs_sds_write_bits(ctrl, 2, 0x1f, 0x2, 15, 0, 53);
                v = rtpcs_sds_read_bits(ctrl, 2, 0x1f, 20, 5, 4);
                if (v == 3)
                        return 0;
-       } while (jiffies < start + (HZ / 1000) * timeout);
+       } while (time_before(jiffies, end));
 
        return 1;
 }