static int
zl3073x_devlink_param_clock_id_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- if (!val.vu64) {
+ if (!val->vu64) {
NL_SET_ERR_MSG_MOD(extack, "'clock_id' must be non-zero");
return -EINVAL;
}
value.vu64 = zldev->clock_id;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_CLOCK_ID,
- value);
+ &value);
/* Register devlink instance */
devl_register(devlink);
#include "ena_phc.h"
static int ena_devlink_enable_phc_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct ena_adapter *adapter = ENA_DEVLINK_PRIV(devlink);
- if (!val.vbool)
+ if (!val->vbool)
return 0;
if (!ena_com_phc_supported(adapter->ena_dev)) {
value.vbool = false;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_ENABLE_PHC,
- value);
+ &value);
devl_unlock(devlink);
}
value.vbool = ena_phc_is_enabled(adapter);
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_ENABLE_PHC,
- value);
+ &value);
devl_unlock(devlink);
return 0;
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack);
int pdsc_dl_enable_validate(struct devlink *dl, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack);
void __iomem *pdsc_map_dbpage(struct pdsc *pdsc, int page_num);
}
int pdsc_dl_enable_validate(struct devlink *dl, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct pdsc *pdsc = devlink_priv(dl);
}
static int bnxt_dl_roce_validate(struct devlink *dl, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
const struct bnxt_dl_nvm_param nvm_roce_cap = {0, NVM_OFF_RDMA_CAPABLE,
}
static int bnxt_dl_msix_validate(struct devlink *dl, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
int max_val = -1;
if (id == DEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN)
max_val = BNXT_MSIX_VEC_MIN_MAX;
- if (val.vu32 > max_val) {
+ if (val->vu32 > max_val) {
NL_SET_ERR_MSG_MOD(extack, "MSIX value is exceeding the range");
return -EINVAL;
}
* error.
*/
static int ice_devlink_tx_sched_layers_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- if (val.vu8 != ICE_SCHED_5_LAYERS && val.vu8 != ICE_SCHED_9_LAYERS) {
+ if (val->vu8 != ICE_SCHED_5_LAYERS && val->vu8 != ICE_SCHED_9_LAYERS) {
NL_SET_ERR_MSG_MOD(extack,
"Wrong number of tx scheduler layers provided.");
return -EINVAL;
static int
ice_devlink_enable_roce_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct ice_pf *pf = devlink_priv(devlink);
static int
ice_devlink_enable_iw_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct ice_pf *pf = devlink_priv(devlink);
* error.
*/
static int ice_devlink_local_fwd_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- if (ice_devlink_local_fwd_str_to_mode(val.vstr) < 0) {
+ if (ice_devlink_local_fwd_str_to_mode(val->vstr) < 0) {
NL_SET_ERR_MSG_MOD(extack, "Error: Requested value is not supported.");
return -EINVAL;
}
static int
ice_devlink_msix_max_pf_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct ice_pf *pf = devlink_priv(devlink);
- if (val.vu32 > pf->hw.func_caps.common_cap.num_msix_vectors)
+ if (val->vu32 > pf->hw.func_caps.common_cap.num_msix_vectors)
return -EINVAL;
return 0;
static int
ice_devlink_msix_min_pf_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- if (val.vu32 < ICE_MIN_MSIX)
+ if (val->vu32 < ICE_MIN_MSIX)
return -EINVAL;
return 0;
}
static int ice_devlink_enable_rdma_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct ice_pf *pf = devlink_priv(devlink);
- bool new_state = val.vbool;
+ bool new_state = val->vbool;
if (new_state && !test_bit(ICE_FLAG_RDMA_ENA, pf->flags))
return -EOPNOTSUPP;
value.vu32 = pf->msix.max;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MAX,
- value);
+ &value);
value.vu32 = pf->msix.min;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_MSIX_VEC_PER_PF_MIN,
- value);
+ &value);
value.vbool = test_bit(ICE_FLAG_RDMA_ENA, pf->flags);
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA,
- value);
+ &value);
return 0;
/* Devlink Params APIs */
static int rvu_af_dl_dwrr_mtu_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct rvu_devlink *rvu_dl = devlink_priv(devlink);
struct rvu *rvu = rvu_dl->rvu;
- int dwrr_mtu = val.vu32;
+ int dwrr_mtu = val->vu32;
struct nix_txsch *txsch;
struct nix_hw *nix_hw;
}
static int rvu_af_npc_defrag_feature_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct rvu_devlink *rvu_dl = devlink_priv(devlink);
struct rvu *rvu = rvu_dl->rvu;
u64 enable;
- if (kstrtoull(val.vstr, 10, &enable)) {
+ if (kstrtoull(val->vstr, 10, &enable)) {
NL_SET_ERR_MSG_MOD(extack,
"Only 1 value is supported");
return -EINVAL;
}
static int rvu_af_npc_exact_feature_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct rvu_devlink *rvu_dl = devlink_priv(devlink);
struct rvu *rvu = rvu_dl->rvu;
u64 enable;
- if (kstrtoull(val.vstr, 10, &enable)) {
+ if (kstrtoull(val->vstr, 10, &enable)) {
NL_SET_ERR_MSG_MOD(extack,
"Only 1 value is supported");
return -EINVAL;
}
static int rvu_af_dl_npc_mcam_high_zone_percent_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct rvu_devlink *rvu_dl = devlink_priv(devlink);
struct npc_mcam *mcam;
/* The percent of high prio zone must range from 12% to 100% of unreserved mcam space */
- if (val.vu8 < 12 || val.vu8 > 100) {
+ if (val->vu8 < 12 || val->vu8 > 100) {
NL_SET_ERR_MSG_MOD(extack,
"mcam high zone percent must be between 12% to 100%");
return -EINVAL;
}
static int rvu_af_dl_nix_maxlf_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct rvu_devlink *rvu_dl = devlink_priv(devlink);
return -EPERM;
}
- if (max_nix0_lf && val.vu16 > max_nix0_lf) {
+ if (max_nix0_lf && val->vu16 > max_nix0_lf) {
NL_SET_ERR_MSG_MOD(extack,
"requested nixlf is greater than the max supported nix0_lf");
return -EPERM;
}
- if (max_nix1_lf && val.vu16 > max_nix1_lf) {
+ if (max_nix1_lf && val->vu16 > max_nix1_lf) {
NL_SET_ERR_MSG_MOD(extack,
"requested nixlf is greater than the max supported nix1_lf");
return -EINVAL;
/* Devlink Params APIs */
static int otx2_dl_mcam_count_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct otx2_devlink *otx2_dl = devlink_priv(devlink);
}
static int otx2_dl_ucast_flt_cnt_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct otx2_devlink *otx2_dl = devlink_priv(devlink);
static int
mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- u32 value = val.vu32;
+ u32 value = val->vu32;
if (value < 1 || value > 128)
return -ERANGE;
value.vbool = !!mlx4_internal_err_reset;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET,
- value);
+ &value);
value.vu32 = 1UL << log_num_mac;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
- value);
+ &value);
value.vbool = enable_64b_cqe_eqe;
devl_param_driverinit_value_set(devlink,
MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
- value);
+ &value);
value.vbool = enable_4k_uar;
devl_param_driverinit_value_set(devlink,
MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
- value);
+ &value);
value.vbool = false;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT,
- value);
+ &value);
}
static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
}
static int mlx5_devlink_enable_roce_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
- bool new_state = val.vbool;
+ bool new_state = val->vbool;
if (new_state && !MLX5_CAP_GEN(dev, roce) &&
!(MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))) {
#ifdef CONFIG_MLX5_ESWITCH
static int mlx5_devlink_large_group_num_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- int group_num = val.vu32;
+ int group_num = val->vu32;
if (group_num < 1 || group_num > 1024) {
NL_SET_ERR_MSG_MOD(extack,
#endif
static int mlx5_devlink_eq_depth_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- return (val.vu32 >= 64 && val.vu32 <= 4096) ? 0 : -EINVAL;
+ return (val->vu32 >= 64 && val->vu32 <= 4096) ? 0 : -EINVAL;
}
static int
mlx5_devlink_hairpin_num_queues_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- return val.vu32 ? 0 : -EINVAL;
+ return val->vu32 ? 0 : -EINVAL;
}
static int
mlx5_devlink_hairpin_queue_size_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
- u32 val32 = val.vu32;
+ u32 val32 = val->vu32;
if (!is_power_of_2(val32)) {
NL_SET_ERR_MSG_MOD(extack, "Value is not power of two");
}
static int mlx5_devlink_num_doorbells_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *mdev = devlink_priv(devlink);
- u32 val32 = val.vu32;
+ u32 val32 = val->vu32;
u32 max_num_channels;
max_num_channels = mlx5e_get_max_num_channels(mdev);
value.vu32 = link_speed64;
devl_param_driverinit_value_set(
- devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, value);
+ devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, &value);
value.vu32 =
BIT(min_t(u32, 16 - MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(dev),
MLX5_CAP_GEN(dev, log_max_hairpin_num_packets)));
devl_param_driverinit_value_set(
- devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, value);
+ devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, &value);
}
static const struct devlink_param mlx5_devlink_params[] = {
value.vbool = MLX5_CAP_GEN(dev, roce) && !mlx5_dev_is_lightweight(dev);
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
- value);
+ &value);
#ifdef CONFIG_MLX5_ESWITCH
value.vu32 = ESW_OFFLOADS_DEFAULT_NUM_GROUPS;
devl_param_driverinit_value_set(devlink,
MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM,
- value);
+ &value);
#endif
value.vu32 = MLX5_COMP_EQ_SIZE;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE,
- value);
+ &value);
value.vu32 = MLX5_NUM_ASYNC_EQE;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE,
- value);
+ &value);
}
static const struct devlink_param mlx5_devlink_eth_params[] = {
value.vbool = !mlx5_dev_is_lightweight(dev);
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_ENABLE_ETH,
- value);
+ &value);
mlx5_devlink_hairpin_params_init_values(devlink);
value.vu32 = MLX5_DEFAULT_NUM_DOORBELLS;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS,
- value);
+ &value);
return 0;
}
static int
mlx5_devlink_pcie_cong_thresh_validate(struct devlink *devl, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- if (val.vu16 > MLX5_PCIE_CONG_THRESH_MAX) {
+ if (val->vu16 > MLX5_PCIE_CONG_THRESH_MAX) {
NL_SET_ERR_MSG_FMT_MOD(extack, "Value %u > max supported (%u)",
- val.vu16, MLX5_PCIE_CONG_THRESH_MAX);
+ val->vu16, MLX5_PCIE_CONG_THRESH_MAX);
return -EINVAL;
}
value.vu16 = MLX5_PCIE_CONG_THRESH_DEF_LOW;
id = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_LOW;
- devl_param_driverinit_value_set(devlink, id, value);
+ devl_param_driverinit_value_set(devlink, id, &value);
value.vu16 = MLX5_PCIE_CONG_THRESH_DEF_HIGH;
id = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_IN_HIGH;
- devl_param_driverinit_value_set(devlink, id, value);
+ devl_param_driverinit_value_set(devlink, id, &value);
value.vu16 = MLX5_PCIE_CONG_THRESH_DEF_LOW;
id = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_LOW;
- devl_param_driverinit_value_set(devlink, id, value);
+ devl_param_driverinit_value_set(devlink, id, &value);
value.vu16 = MLX5_PCIE_CONG_THRESH_DEF_HIGH;
id = MLX5_DEVLINK_PARAM_ID_PCIE_CONG_OUT_HIGH;
- devl_param_driverinit_value_set(devlink, id, value);
+ devl_param_driverinit_value_set(devlink, id, &value);
}
static const struct devlink_param mlx5_devlink_pcie_cong_params[] = {
}
static int mlx5_devlink_enable_rdma_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
- bool new_state = val.vbool;
+ bool new_state = val->vbool;
if (new_state && !mlx5_rdma_supported(dev))
return -EOPNOTSUPP;
value.vbool = !mlx5_dev_is_lightweight(dev);
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA,
- value);
+ &value);
return 0;
}
value.vbool = !mlx5_dev_is_lightweight(dev);
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_ENABLE_VNET,
- value);
+ &value);
return 0;
}
}
static int mlx5_devlink_max_uc_list_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
- if (val.vu32 == 0) {
+ if (val->vu32 == 0) {
NL_SET_ERR_MSG_MOD(extack, "max_macs value must be greater than 0");
return -EINVAL;
}
- if (!is_power_of_2(val.vu32)) {
+ if (!is_power_of_2(val->vu32)) {
NL_SET_ERR_MSG_MOD(extack, "Only power of 2 values are supported for max_macs");
return -EINVAL;
}
- if (ilog2(val.vu32) >
+ if (ilog2(val->vu32) >
MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list)) {
NL_SET_ERR_MSG_MOD(extack, "max_macs value is out of the supported range");
return -EINVAL;
value.vu32 = 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list);
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
- value);
+ &value);
return 0;
}
}
static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
}
static int mlx5_fs_mode_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
- char *value = val.vstr;
+ char *value = val->vstr;
u8 eswitch_mode;
eswitch_mode = mlx5_eswitch_mode(dev);
static int
mlx5_nv_param_devlink_cqe_compress_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
int i;
for (i = 0; i < ARRAY_SIZE(cqe_compress_str); i++) {
- if (!strcmp(val.vstr, cqe_compress_str[i]))
+ if (!strcmp(val->vstr, cqe_compress_str[i]))
return 0;
}
static int
mlx5_devlink_swp_l4_csum_mode_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
int err, i;
for (i = 0; i < ARRAY_SIZE(swp_l4_csum_mode_str); i++) {
- if (!strcmp(val.vstr, swp_l4_csum_mode_str[i]))
+ if (!strcmp(val->vstr, swp_l4_csum_mode_str[i]))
break;
}
}
static int mlx5_devlink_total_vfs_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
return 0; /* optimistic, but set might fail later */
max = MLX5_GET(nv_global_pci_cap, data, max_vfs_per_pf);
- if (val.vu16 > max) {
+ if (val->vu16 > max) {
NL_SET_ERR_MSG_FMT_MOD(extack,
"Max allowed by device is %u", max);
return -EINVAL;
}
static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
- if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER &&
- val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) {
+ if (val->vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER &&
+ val->vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) {
NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
return -EINVAL;
}
value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
- value);
+ &value);
return 0;
}
static int
nfp_devlink_param_u8_validate(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack)
{
const struct nfp_devlink_param_u8_arg *arg;
arg = &nfp_devlink_u8_args[id];
- if (val.vu8 > arg->max_dl_val) {
+ if (val->vu8 > arg->max_dl_val) {
NL_SET_ERR_MSG_MOD(extack, "parameter out of range");
return -EINVAL;
}
- if (val.vu8 == arg->invalid_dl_val) {
+ if (val->vu8 == arg->invalid_dl_val) {
NL_SET_ERR_MSG_MOD(extack, "unknown/invalid value specified");
return -EINVAL;
}
value.vu32 = nsim_dev->max_macs;
devl_param_driverinit_value_set(devlink,
DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
- value);
+ &value);
value.vbool = nsim_dev->test1;
devl_param_driverinit_value_set(devlink,
NSIM_DEVLINK_PARAM_ID_TEST1,
- value);
+ &value);
}
static void nsim_devlink_param_load_driverinit_values(struct devlink *devlink)
struct devlink_param_gset_ctx *ctx,
struct netlink_ext_ack *extack);
int (*validate)(struct devlink *devlink, u32 id,
- union devlink_param_value val,
+ union devlink_param_value *val,
struct netlink_ext_ack *extack);
int (*get_default)(struct devlink *devlink, u32 id,
struct devlink_param_gset_ctx *ctx,
int devl_param_driverinit_value_get(struct devlink *devlink, u32 param_id,
union devlink_param_value *val);
void devl_param_driverinit_value_set(struct devlink *devlink, u32 param_id,
- union devlink_param_value init_val);
+ union devlink_param_value *init_val);
void devl_param_value_changed(struct devlink *devlink, u32 param_id);
struct devlink_region *devl_region_create(struct devlink *devlink,
const struct devlink_region_ops *ops,
static int
devlink_nl_param_value_put(struct sk_buff *msg, enum devlink_param_type type,
- int nla_type, union devlink_param_value val,
+ int nla_type, union devlink_param_value *val,
bool flag_as_u8)
{
switch (type) {
case DEVLINK_PARAM_TYPE_U8:
- if (nla_put_u8(msg, nla_type, val.vu8))
+ if (nla_put_u8(msg, nla_type, val->vu8))
return -EMSGSIZE;
break;
case DEVLINK_PARAM_TYPE_U16:
- if (nla_put_u16(msg, nla_type, val.vu16))
+ if (nla_put_u16(msg, nla_type, val->vu16))
return -EMSGSIZE;
break;
case DEVLINK_PARAM_TYPE_U32:
- if (nla_put_u32(msg, nla_type, val.vu32))
+ if (nla_put_u32(msg, nla_type, val->vu32))
return -EMSGSIZE;
break;
case DEVLINK_PARAM_TYPE_U64:
- if (devlink_nl_put_u64(msg, nla_type, val.vu64))
+ if (devlink_nl_put_u64(msg, nla_type, val->vu64))
return -EMSGSIZE;
break;
case DEVLINK_PARAM_TYPE_STRING:
- if (nla_put_string(msg, nla_type, val.vstr))
+ if (nla_put_string(msg, nla_type, val->vstr))
return -EMSGSIZE;
break;
case DEVLINK_PARAM_TYPE_BOOL:
* false can be distinguished from not present
*/
if (flag_as_u8) {
- if (nla_put_u8(msg, nla_type, val.vbool))
+ if (nla_put_u8(msg, nla_type, val->vbool))
return -EMSGSIZE;
} else {
- if (val.vbool && nla_put_flag(msg, nla_type))
+ if (val->vbool && nla_put_flag(msg, nla_type))
return -EMSGSIZE;
}
break;
devlink_nl_param_value_fill_one(struct sk_buff *msg,
enum devlink_param_type type,
enum devlink_param_cmode cmode,
- union devlink_param_value val,
- union devlink_param_value default_val,
+ union devlink_param_value *val,
+ union devlink_param_value *default_val,
bool has_default)
{
struct nlattr *param_value_attr;
if (!param_value_set[i])
continue;
err = devlink_nl_param_value_fill_one(msg, param->type,
- i, param_value[i],
- default_value[i],
+ i, ¶m_value[i],
+ &default_value[i],
default_value_set[i]);
if (err)
goto values_list_nest_cancel;
if (err)
return err;
if (param->validate) {
- err = param->validate(devlink, param->id, value,
+ err = param->validate(devlink, param->id, &value,
info->extack);
if (err)
return err;
* configuration mode default value.
*/
void devl_param_driverinit_value_set(struct devlink *devlink, u32 param_id,
- union devlink_param_value init_val)
+ union devlink_param_value *init_val)
{
struct devlink_param_item *param_item;
DEVLINK_PARAM_CMODE_DRIVERINIT)))
return;
- param_item->driverinit_value = init_val;
+ param_item->driverinit_value = *init_val;
param_item->driverinit_value_valid = true;
- param_item->driverinit_default = init_val;
+ param_item->driverinit_default = *init_val;
devlink_param_notify(devlink, 0, param_item, DEVLINK_CMD_PARAM_NEW);
}