arm: agilex5: Enable SD card UHS mode support

Enable Ultra High Speed (UHS-I) mode support for SD cards on
Agilex5 SoC development kit.

Defconfig changes:
- Enable CONFIG_MMC_UHS_SUPPORT and CONFIG_SPL_MMC_UHS_SUPPORT

Device tree changes:
- Remove no-1-8-v to allow 1.8V signaling for UHS modes
- Add sd-uhs-sdr50 and sd-uhs-sdr104 capabilities
- Add sdhci-caps and sdhci-caps-mask for proper capability reporting
- Add PHY and controller timing configuration

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index b443e57b1cd38e55cb63ab304e3930416678ee70..c03f78b2fdf76c326f6d9e0debb7085c626eccc6 100644 (file)
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -110,12 +110,15 @@
        status = "okay";
 
        no-mmc;
-       no-1-8-v;
        disable-wp;
        cap-sd-highspeed;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
        vmmc-supply = <&sd_emmc_power>;
        vqmmc-supply = <&sd_io_1v8_reg>;
        max-frequency = <200000000>;
+       sdhci-caps = <0x00000000 0x0000c800>;
+       sdhci-caps-mask = <0x00002000 0x0000ff00>;
 
        /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */
        cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
@@ -130,6 +133,26 @@
        cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>;
        cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>;
 
+       /* SD card UHS-I SDR50 mode timing configuration */
+       cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>;
+       cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>;
+       cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>;
+       cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>;
+       cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>;
+       cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>;
+       cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
+       cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>;
+
+       /* SD card UHS-I SDR104 mode timing configuration */
+       cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>;
+       cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>;
+       cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>;
+       cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>;
+       cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>;
+       cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>;
+       cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
+       cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
+
        bootph-all;
 };
 

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 5fbc49b2307943fd16c1529ec9c576df43be9187..8a3f9563af2041fa879eb27cd5f619933e882724 100644 (file)
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -87,6 +87,8 @@ CONFIG_DW_I3C_MASTER=y
 CONFIG_MISC=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y