mips64: add a workaround for Cavium CPUs to support mips32r1-r2-mips64r1

Linux kernel incorrectly shows that MIPS Cavium CPUs do not support mips32r1,
mips32r2 and mips64r1. This is due to incorrect defines in

arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h

that affect show_cpuinfo() function.

Until that is changed in Linux kernel, we need a workaround in Valgrind, so
all supported ISAs can be executed correctly.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16390

diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index eac1c167dcddb5cd73673e41437be8b1db39032d..893c32e1f3190e8f5ad65ae1241b2d554467eb1f 100644 (file)
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -726,6 +726,18 @@ static Bool VG_(parse_cpuinfo)(void)
           vai.hwcaps |= VEX_MIPS_CPU_ISA_M64R2;
       if (VG_(strstr) (isa, "mips64r6") != NULL)
           vai.hwcaps |= VEX_MIPS_CPU_ISA_M64R6;
+
+      /*
+       * TODO(petarj): Remove this Cavium workaround once Linux kernel folks
+       * decide to change incorrect settings in
+       * mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h.
+       * The current settings show mips32r1, mips32r2 and mips64r1 as
+       * unsupported ISAs by Cavium MIPS CPUs.
+       */
+      if (VEX_MIPS_COMP_ID(vai.hwcaps) == VEX_PRID_COMP_CAVIUM) {
+         vai.hwcaps |= VEX_MIPS_CPU_ISA_M32R1 | VEX_MIPS_CPU_ISA_M32R2 |
+                       VEX_MIPS_CPU_ISA_M64R1;
+      }
    } else {
       /*
        * Kernel does not provide information about supported ISAs.