[PATCH v2] RISC-V: Fix gcc.target/riscv/rvv/base/cpymem-1.c f3

The function body checks for f3 only ran with -mcmodel explicitly set
which meant I missed a regression in my local testing of:

  commit b039d06c9a810a3fab4c5eb9d50b0c7aff94b2d8
  Author: Craig Blackmore <craig.blackmore@embecosm.com>
  Date:   Fri Oct 18 09:17:21 2024 -0600

      [PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generation

The failure showed up in the rivos CI and it is due to f3 now using
LMUL m1 instead of m8.

I have reworked the test to make it more robust and maintainable.  This
allowed most of the special casing of command line arguments to be
removed.  It also fixes an issue where some targets would enable
multiple versions of the function body check e.g. `-march=rv32gcv
-mcmodel=medany`.

Changes since v1: Added missing ChangeLog.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/cpymem-1.c: Fix and rework f3.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 6edb4c9253a4b65562c96b56ef96f15d557d9983..81d14d83633420fa51f5c0ff576a79999da70d0c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -9,6 +9,8 @@
 extern void *memcpy(void *__restrict dest, const void *__restrict src, __SIZE_TYPE__ n);
 #endif
 
+#define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8)
+
 /* memcpy should be implemented using the cpymem pattern.
 ** f1:
 XX     \.L\d+: # local label is ignored
@@ -50,70 +52,57 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
    Use extern here so that we get a known alignment, lest
    DATA_ALIGNMENT force us to make the scan pattern accomodate
    code for different alignments depending on word size.
-** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m2" "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-vector-bits=zvl" } } }
-**        lui\s+[ta][0-7],%hi\(a_a\)
-**        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
-**        lui\s+[ta][0-7],%hi\(a_b\)
-**        addi\s+a4,[ta][0-7],%lo\(a_b\)
-**        vsetivli\s+zero,16,e32,m8,ta,ma
-**        vle32.v\s+v\d+,0\([ta][0-7]\)
-**        vse32\.v\s+v\d+,0\([ta][0-7]\)
-**        ret
-*/
-
-/*
-** f3: { target { { any-opts "-mcmodel=medlow -mrvv-vector-bits=zvl" "-mcmodel=medlow -march=rv64gcv_zvl512b -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } }
-**        lui\s+[ta][0-7],%hi\(a_a\)
-**        lui\s+[ta][0-7],%hi\(a_b\)
-**        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
-**        addi\s+a4,[ta][0-7],%lo\(a_b\)
-**        vl(1|4|2)re32\.v\s+v\d+,0\([ta][0-7]\)
-**        vs(1|4|2)r\.v\s+v\d+,0\([ta][0-7]\)
-**        ret
-*/
-
-/*
-** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "-mrvv-vector-bits=zvl" } } }
-**        lui\s+[ta][0-7],%hi\(a_a\)
-**        lui\s+[ta][0-7],%hi\(a_b\)
-**        addi\s+a4,[ta][0-7],%lo\(a_b\)
-**        vsetivli\s+zero,16,e32,(m1|m4|mf2),ta,ma
-**        vle32.v\s+v\d+,0\([ta][0-7]\)
-**        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
-**        vse32\.v\s+v\d+,0\([ta][0-7]\)
-**        ret
-*/
-
-/*
-** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=m4" "-mrvv-vector-bits=zvl" } } }
-**        lla\s+[ta][0-7],a_a
-**        lla\s+[ta][0-7],a_b
-**        vsetivli\s+zero,16,e32,m8,ta,ma
-**        vle32.v\s+v\d+,0\([ta][0-7]\)
-**        vse32\.v\s+v\d+,0\([ta][0-7]\)
-**        ret
-*/
-
-/*
-** f3: { target { { any-opts "-mcmodel=medany"  } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv" "-march=rv64gc_zve64d" "-march=rv64gc_zve32f" } } }
-**        lla\s+[ta][0-7],a_b
-**        vsetivli\s+zero,16,e32,m(f2|1|4),ta,ma
-**        vle32.v\s+v\d+,0\([ta][0-7]\)
-**        lla\s+[ta][0-7],a_a
-**        vse32\.v\s+v\d+,0\([ta][0-7]\)
-**        ret
+** f3: { target { no-opts "-mrvv-vector-bits=zvl" } }
+**  (
+**  lui\s+[ta][0-7],%hi\(a_a\)
+**  lui\s+[ta][0-7],%hi\(a_b\)
+**  addi\s+[ta][0-7],[ta][0-7],%lo\(a_b\)
+**  vsetivli\s+zero,4,e32,m1,ta,ma
+**  |
+**  lui\s+[ta][0-7],%hi\(a_a\)
+**  lui\s+[ta][0-7],%hi\(a_b\)
+**  li\s+[ta][0-7],\d+
+**  addi\s+[ta][0-7],[ta][0-7],%lo\(a_b\)
+**  vsetvli\s+zero,[ta][0-7],e32,m1,ta,ma
+**  |
+**  lla\s+[ta][0-7],a_b
+**  vsetivli\s+zero,4,e32,m1,ta,ma
+**  |
+**  li\s+[ta][0-7],\d+
+**  lla\s+[ta][0-7],a_b
+**  vsetvli\s+zero,[ta][0-7],e32,m1,ta,ma
+**  |
+**  lla\s+[ta][0-7],a_b
+**  li\s+[ta][0-7],32
+**  vsetvli\s+zero,[ta][0-7],e32,m1,ta,ma
+**  )
+**  vle32.v\s+v\d+,0\([ta][0-7]\)
+**  (
+**  addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
+**  |
+**  lla\s+[ta][0-7],a_a
+**  )
+**  vse32.v\s+v\d+,0\([ta][0-7]\)
+**  ret
 */
 
 /*
-** f3: { target { { any-opts "-mcmodel=medany -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } }
-**        lla\s+[ta][0-7],a_a
-**        lla\s+[ta][0-7],a_b
-**        vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\)
-**        vs(1|2|4)r\.v\s+v\d+,0\([ta][0-7]\)
-**        ret
+** f3: { target { any-opts "-mrvv-vector-bits=zvl" } }
+**  (
+**  lui\s+[ta][0-7],%hi\(a_a\)
+**  lui\s+[ta][0-7],%hi\(a_b\)
+**  addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
+**  addi\s+[ta][0-7],[ta][0-7],%lo\(a_b\)
+**  |
+**  lla\s+[ta][0-7],a_a
+**  lla\s+[ta][0-7],a_b
+**  )
+**  vl1re32.v\s+v\d+,0\([ta][0-7]\)
+**  vs1r.v\s+v\d+,0\([ta][0-7]\)
+**  ret
 */
 
-extern struct { __INT32_TYPE__ a[16]; } a_a, a_b;
+extern struct { __INT32_TYPE__ a[MIN_VECTOR_BYTES / 4]; } a_a, a_b;
 
 void f3 ()
 {