AMDGIM_FEATURE_RAS_CPER = (1 << 11),
AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12),
AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13),
+ AMDGIM_FEATURE_PTL_SUPPORT = (1 << 14),
+ AMDGIM_FEATURE_UNITID_SUPPORT = (1 << 15),
};
enum AMDGIM_REG_ACCESS_FLAG {
((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
#define amdgpu_sriov_is_mes_info_enable(adev) \
((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE)
+#define amdgpu_sriov_is_unitid_support(adev) \
+ ((adev)->virt.gim_feature & AMDGIM_FEATURE_UNITID_SUPPORT)
#define amdgpu_virt_xgmi_migrate_enabled(adev) \
((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0)
uint32_t ras_cper : 1;
uint32_t xgmi_ta_ext_peer_link : 1;
uint32_t xgmi_connected_to_cpu : 1;
- uint32_t reserved : 18;
+ uint32_t ptl_support : 1;
+ uint32_t unitid_support : 1;
+ uint32_t reserved : 16;
} flags;
uint32_t all;
};
uint32_t reserved[2];
};
-#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55)
+#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (59)
struct amd_sriov_msg_pf2vf_info {
/* header contains size and version */
struct amd_sriov_msg_pf2vf_info_header header;
uint32_t more_bp; //Reserved for future use.
union amd_sriov_ras_caps ras_en_caps;
union amd_sriov_ras_caps ras_telemetry_en_caps;
+ /* PTL status response for guest */
+ uint32_t ptl_enabled; // PTL enable status: 0=disabled, 1=enabled
+ uint32_t ptl_pref_format1; // Current preferred format 1
+ uint32_t ptl_pref_format2; // Current preferred format 2
+ /* unit ID assigned by host; vf_idx [0..254] maps to unitid [1..255] (0 = pf) */
+ uint8_t unitid;
+ uint8_t padding[3]; //use the 3 bytes to align
/* reserved */
uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];