6.18-stable patches

added patches:
	drm-i915-psr-compute-psr-entry_setup_frames-into-intel_crtc_state.patch

diff --git a/queue-6.18/drm-i915-psr-compute-psr-entry_setup_frames-into-intel_crtc_state.patch b/queue-6.18/drm-i915-psr-compute-psr-entry_setup_frames-into-intel_crtc_state.patch
new file mode 100644 (file)
index 0000000..8eae63a
--- /dev/null
+++ b/queue-6.18/drm-i915-psr-compute-psr-entry_setup_frames-into-intel_crtc_state.patch
@@ -0,0 +1,73 @@
+From 7caac659a837af9fd4cad85be851982b88859484 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <jouni.hogander@intel.com>
+Date: Thu, 12 Mar 2026 10:37:10 +0200
+Subject: drm/i915/psr: Compute PSR entry_setup_frames into intel_crtc_state
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jouni Högander <jouni.hogander@intel.com>
+
+commit 7caac659a837af9fd4cad85be851982b88859484 upstream.
+
+PSR entry_setup_frames is currently computed directly into struct
+intel_dp:intel_psr:entry_setup_frames. This causes a problem if mode change
+gets rejected after PSR compute config: Psr_entry_setup_frames computed for
+this rejected state is in intel_dp:intel_psr:entry_setup_frame. Fix this by
+computing it into intel_crtc_state and copy the value into
+intel_dp:intel_psr:entry_setup_frames on PSR enable.
+
+Fixes: 2b981d57e480 ("drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier")
+Cc: Mika Kahola <mika.kahola@intel.com>
+Cc: <stable@vger.kernel.org> # v6.8+
+Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
+Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Link: https://patch.msgid.link/20260312083710.1593781-3-jouni.hogander@intel.com
+(cherry picked from commit 8c229b4aa00262c13787982e998c61c0783285e0)
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+[ adapted context lines to account for missing `no_psr_reason` field and `alpm_state` struct. ]
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_display_types.h |    1 +
+ drivers/gpu/drm/i915/display/intel_psr.c           |    5 +++--
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_display_types.h
++++ b/drivers/gpu/drm/i915/display/intel_display_types.h
+@@ -1127,6 +1127,7 @@ struct intel_crtc_state {
+       u32 dc3co_exitline;
+       u16 su_y_granularity;
+       u8 active_non_psr_pipes;
++      u8 entry_setup_frames;
+ 
+       /*
+        * Frequency the dpll for the port should run at. Differs from the
+--- a/drivers/gpu/drm/i915/display/intel_psr.c
++++ b/drivers/gpu/drm/i915/display/intel_psr.c
+@@ -1585,7 +1585,7 @@ static bool _psr_compute_config(struct i
+       entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
+ 
+       if (entry_setup_frames >= 0) {
+-              intel_dp->psr.entry_setup_frames = entry_setup_frames;
++              crtc_state->entry_setup_frames = entry_setup_frames;
+       } else {
+               drm_dbg_kms(display->drm,
+                           "PSR condition failed: PSR setup timing not met\n");
+@@ -1657,7 +1657,7 @@ static bool intel_psr_needs_wa_180378188
+ {
+       struct intel_display *display = to_intel_display(intel_dp);
+ 
+-      return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 &&
++      return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&
+               !crtc_state->has_sel_update);
+ }
+ 
+@@ -2027,6 +2027,7 @@ static void intel_psr_enable_locked(stru
+               crtc_state->req_psr2_sdp_prior_scanline;
+       intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
+       intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
++      intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
+ 
+       if (!psr_interrupt_error_check(intel_dp))
+               return;

diff --git a/queue-6.18/series b/queue-6.18/series
index f2ffb8546e0155abd629b74a7cf0209675d68a2f..d21ebe4715b6d7ea50adb1972433f50f0bebcb6a 100644 (file)
--- a/queue-6.18/series
+++ b/queue-6.18/series
@@ -95,3 +95,4 @@ drm-xe-guc-ensure-ct-state-transitions-via-stop-before-disabled.patch
 drm-xe-oa-allow-reading-after-disabling-oa-stream.patch
 drm-xe-open-code-ggtt-mmio-access-protection.patch
 bluetooth-l2cap-fix-accepting-multiple-l2cap_ecred_conn_req.patch
+drm-i915-psr-compute-psr-entry_setup_frames-into-intel_crtc_state.patch