arm64: dts: rockchip: Add vop for rk3576

Add VOP and VOP_MMU found on rk3576.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20241231095728.253943-2-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 29b47799849ad50540755d62622865d84226c6c4..943a40dca835e3eca9603904200b3d38cce6631f 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -393,6 +393,11 @@
                };
        };
 
+       display_subsystem: display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vop_out>;
+       };
+
        firmware {
                scmi: scmi {
                        compatible = "arm,scmi-smc";
@@ -937,6 +942,69 @@
                        status = "disabled";
                };
 
+               vop: vop@27d00000 {
+                       compatible = "rockchip,rk3576-vop";
+                       reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
+                       reg-names = "vop", "gamma-lut";
+                       interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "sys",
+                                         "vp0",
+                                         "vp1",
+                                         "vp2";
+                       clocks = <&cru ACLK_VOP>,
+                                <&cru HCLK_VOP>,
+                                <&cru DCLK_VP0>,
+                                <&cru DCLK_VP1>,
+                                <&cru DCLK_VP2>;
+                       clock-names = "aclk",
+                                     "hclk",
+                                     "dclk_vp0",
+                                     "dclk_vp1",
+                                     "dclk_vp2";
+                       iommus = <&vop_mmu>;
+                       power-domains = <&power RK3576_PD_VOP>;
+                       rockchip,grf = <&sys_grf>;
+                       rockchip,pmu = <&pmu>;
+                       status = "disabled";
+
+                       vop_out: ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               vp0: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+                               };
+
+                               vp1: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+                               };
+
+                               vp2: port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <2>;
+                               };
+                       };
+               };
+
+               vop_mmu: iommu@27d07e00 {
+                       compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
+                       reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
+                       interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+                       clock-names = "aclk", "iface";
+                       #iommu-cells = <0>;
+                       power-domains = <&power RK3576_PD_VOP>;
+                       status = "disabled";
+               };
+
                qos_hdcp1: qos@27f02000 {
                        compatible = "rockchip,rk3576-qos", "syscon";
                        reg = <0x0 0x27f02000 0x0 0x20>;