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[multiple changes]
authorH.J. Lu <hjl@gcc.gnu.org>
Fri, 6 Feb 2004 19:43:33 +0000 (11:43 -0800)
committerH.J. Lu <hjl@gcc.gnu.org>
Fri, 6 Feb 2004 19:43:33 +0000 (11:43 -0800)
2004-02-06  H.J. Lu  <hongjiu.lu@intel.com>

* doc/invoke.texi: Mention SSE2 and SSE3.

* config/i386/i386.h: Deprecate -mpni/-mno-pni.

2004-02-06  Kelley Cook  <kcook@gcc.gnu.org>

* config/i386/i386.c: Rename pni to sse3.
* config/i386/i386.h: Likewise.
        * config/i386/i386.md: Likewise.
* config/i386/pmmintrin.h: Likewise.
* doc/extend.texi: Likewise.
* doc/invoke.texi: Likewise.

From-SVN: r77416

gcc/ChangeLog patch | blob | blame | history
gcc/config/i386/i386.c patch | blob | blame | history
gcc/config/i386/i386.h patch | blob | blame | history
gcc/config/i386/i386.md patch | blob | blame | history
gcc/config/i386/pmmintrin.h patch | blob | blame | history
gcc/doc/extend.texi patch | blob | blame | history
gcc/doc/invoke.texi patch | blob | blame | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4f5d77a31a0db996d777b97b270d466e0151a8ef..b88d4f39f107da9b854b8531f9d5c39679a110e8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2004-02-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * doc/invoke.texi: Mention SSE2 and SSE3.
+
+       * config/i386/i386.h: Deprecate -mpni/-mno-pni.
+
+2004-02-06  Kelley Cook  <kcook@gcc.gnu.org>
+
+       * config/i386/i386.c: Rename pni to sse3.
+       * config/i386/i386.h: Likewise.
+        * config/i386/i386.md: Likewise.
+       * config/i386/pmmintrin.h: Likewise.
+       * doc/extend.texi: Likewise.
+       * doc/invoke.texi: Likewise.
+
 2004-02-03  Wolfgang Bangerth  <bangerth@dealii.org>
 
        PR other/14003
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a3e00e58f9b11cd98a93432d318d08b7579a7187..68a393528a672ee4211974252864abaf7a82b719 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1257,8 +1257,8 @@ override_options ()
   if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
     target_flags &= ~MASK_NO_FANCY_MATH_387;
 
-  /* Turn on SSE2 builtins for -mpni.  */
-  if (TARGET_PNI)
+  /* Turn on SSE2 builtins for -msse3.  */
+  if (TARGET_SSE3)
     target_flags |= MASK_SSE2;
 
   /* Turn on SSE builtins for -msse2.  */
@@ -12397,13 +12397,13 @@ static const struct builtin_description bdesc_2arg[] =
   { MASK_SSE2, CODE_FOR_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
   { MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
 
-  /* PNI MMX */
-  { MASK_PNI, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
-  { MASK_PNI, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
-  { MASK_PNI, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
-  { MASK_PNI, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
-  { MASK_PNI, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
-  { MASK_PNI, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
+  /* SSE3 MMX */
+  { MASK_SSE3, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
+  { MASK_SSE3, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
+  { MASK_SSE3, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
+  { MASK_SSE3, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
+  { MASK_SSE3, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
+  { MASK_SSE3, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
 };
 
 static const struct builtin_description bdesc_1arg[] =
@@ -12451,10 +12451,10 @@ static const struct builtin_description bdesc_1arg[] =
 
   { MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 },
 
-  /* PNI */
-  { MASK_PNI, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
-  { MASK_PNI, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
-  { MASK_PNI, CODE_FOR_movddup,  0, IX86_BUILTIN_MOVDDUP, 0, 0 }
+  /* SSE3 */
+  { MASK_SSE3, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
+  { MASK_SSE3, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
+  { MASK_SSE3, CODE_FOR_movddup,  0, IX86_BUILTIN_MOVDDUP, 0, 0 }
 };
 
 void
@@ -13059,23 +13059,23 @@ ix86_init_mmx_sse_builtins ()
   def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
 
   /* Prescott New Instructions.  */
-  def_builtin (MASK_PNI, "__builtin_ia32_monitor",
+  def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
               void_ftype_pcvoid_unsigned_unsigned,
               IX86_BUILTIN_MONITOR);
-  def_builtin (MASK_PNI, "__builtin_ia32_mwait",
+  def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
               void_ftype_unsigned_unsigned,
               IX86_BUILTIN_MWAIT);
-  def_builtin (MASK_PNI, "__builtin_ia32_movshdup",
+  def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
               v4sf_ftype_v4sf,
               IX86_BUILTIN_MOVSHDUP);
-  def_builtin (MASK_PNI, "__builtin_ia32_movsldup",
+  def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
               v4sf_ftype_v4sf,
               IX86_BUILTIN_MOVSLDUP);
-  def_builtin (MASK_PNI, "__builtin_ia32_lddqu",
+  def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
               v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
-  def_builtin (MASK_PNI, "__builtin_ia32_loadddup",
+  def_builtin (MASK_SSE3, "__builtin_ia32_loadddup",
               v2df_ftype_pcdouble, IX86_BUILTIN_LOADDDUP);
-  def_builtin (MASK_PNI, "__builtin_ia32_movddup",
+  def_builtin (MASK_SSE3, "__builtin_ia32_movddup",
               v2df_ftype_v2df, IX86_BUILTIN_MOVDDUP);
 }
 
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 32bc5d0252ee7fa2f4ad74f92d3bf541483be413..796b48bf347b8eba2b91a6b43109dde1a28c756e 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -114,7 +114,7 @@ extern int target_flags;
 #define MASK_MMX               0x00002000      /* Support MMX regs/builtins */
 #define MASK_SSE               0x00004000      /* Support SSE regs/builtins */
 #define MASK_SSE2              0x00008000      /* Support SSE2 regs/builtins */
-#define MASK_PNI               0x00010000      /* Support PNI builtins */
+#define MASK_SSE3              0x00010000      /* Support SSE3 builtins */
 #define MASK_3DNOW             0x00020000      /* Support 3Dnow builtins */
 #define MASK_3DNOW_A           0x00040000      /* Support Athlon 3Dnow builtins */
 #define MASK_128BIT_LONG_DOUBLE 0x00080000     /* long double size is 128bit */
@@ -274,7 +274,7 @@ extern int x86_prefetch_sse;
 
 #define TARGET_SSE ((target_flags & MASK_SSE) != 0)
 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
-#define TARGET_PNI ((target_flags & MASK_PNI) != 0)
+#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
                             && (ix86_fpmath & FPMATH_387))
@@ -302,6 +302,8 @@ extern int x86_prefetch_sse;
   { "486",                      0, "" /*Deprecated.*/},                      \
   { "pentium",                  0, "" /*Deprecated.*/},                      \
   { "pentiumpro",               0, "" /*Deprecated.*/},                      \
+  { "pni",                      0, "" /*Deprecated.*/},                      \
+  { "no-pni",                   0, "" /*Deprecated.*/},                      \
   { "intel-syntax",             0, "" /*Deprecated.*/},                      \
   { "no-intel-syntax",          0, "" /*Deprecated.*/},                      \
   { "rtd",                      MASK_RTD,                                    \
@@ -368,10 +370,10 @@ extern int x86_prefetch_sse;
     N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
   { "no-sse2",                  -MASK_SSE2,                                  \
     N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") },    \
-  { "pni",                      MASK_PNI,                                    \
-    N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") }, \
-  { "no-pni",                   -MASK_PNI,                                   \
-    N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") }, \
+  { "sse3",                     MASK_SSE3,                                   \
+    N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") }, \
+  { "no-sse3",                  -MASK_SSE3,                                  \
+    N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") }, \
   { "128bit-long-double",       MASK_128BIT_LONG_DOUBLE,                     \
     N_("sizeof(long double) is 16") },                                       \
   { "96bit-long-double",       -MASK_128BIT_LONG_DOUBLE,                     \
@@ -475,6 +477,10 @@ extern int x86_prefetch_sse;
 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
 %{mpentiumpro:-mcpu=pentiumpro \
 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
+%{mpni:-msse3 \
+%n`-mpni' is deprecated. Use `-msse3' instead.\n} \
+%{mno-pni:-mno-sse3 \
+%n`-mno-pni' is deprecated. Use `-mno-sse3' instead.\n} \
 %{mintel-syntax:-masm=intel \
 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
 %{mno-intel-syntax:-masm=att \
@@ -560,8 +566,11 @@ extern int x86_prefetch_sse;
        builtin_define ("__SSE__");                             \
       if (TARGET_SSE2)                                         \
        builtin_define ("__SSE2__");                            \
-      if (TARGET_PNI)                                          \
-       builtin_define ("__PNI__");                             \
+      if (TARGET_SSE3)                                         \
+       {                                                       \
+         builtin_define ("__SSE3__");                          \
+         builtin_define ("__PNI__");                           \
+       }                                                       \
       if (TARGET_SSE_MATH && TARGET_SSE)                       \
        builtin_define ("__SSE_MATH__");                        \
       if (TARGET_SSE_MATH && TARGET_SSE2)                      \
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2e3adab0eeec543735332ae4a82ffa0efa859dfb..6c4e7f0be1edb2ba6831e22d3b2e931660552ab2 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -22082,13 +22082,13 @@
   [(set_attr "type" "sse")
    (set_attr "memory" "unknown")])
 
-;; PNI
+;; SSE3
 
 (define_insn "mwait"
   [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
                     (match_operand:SI 1 "register_operand" "c")]
                    UNSPECV_MWAIT)]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "mwait\t%0, %1"
   [(set_attr "length" "3")])
 
@@ -22097,18 +22097,18 @@
                     (match_operand:SI 1 "register_operand" "c")
                     (match_operand:SI 2 "register_operand" "d")]
                    UNSPECV_MONITOR)]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "monitor\t%0, %1, %2"
   [(set_attr "length" "3")])
 
-;; PNI arithmetic
+;; SSE3 arithmetic
 
 (define_insn "addsubv4sf3"
   [(set (match_operand:V4SF 0 "register_operand" "=x")
         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
                      (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
                     UNSPEC_ADDSUB))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "addsubps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
    (set_attr "mode" "V4SF")])
@@ -22118,7 +22118,7 @@
         (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
                      (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
                     UNSPEC_ADDSUB))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "addsubpd\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
    (set_attr "mode" "V2DF")])
@@ -22128,7 +22128,7 @@
         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
                      (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
                     UNSPEC_HADD))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "haddps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
    (set_attr "mode" "V4SF")])
@@ -22138,7 +22138,7 @@
         (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
                      (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
                     UNSPEC_HADD))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "haddpd\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
    (set_attr "mode" "V2DF")])
@@ -22148,7 +22148,7 @@
         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
                      (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
                     UNSPEC_HSUB))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "hsubps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
    (set_attr "mode" "V4SF")])
@@ -22158,7 +22158,7 @@
         (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
                      (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
                     UNSPEC_HSUB))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "hsubpd\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
    (set_attr "mode" "V2DF")])
@@ -22167,7 +22167,7 @@
   [(set (match_operand:V4SF 0 "register_operand" "=x")
         (unspec:V4SF
         [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "movshdup\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "V4SF")])
@@ -22176,7 +22176,7 @@
   [(set (match_operand:V4SF 0 "register_operand" "=x")
         (unspec:V4SF
         [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "movsldup\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "V4SF")])
@@ -22185,7 +22185,7 @@
   [(set (match_operand:V16QI 0 "register_operand" "=x")
        (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
                       UNSPEC_LDQQU))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "lddqu\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "mode" "TI")])
@@ -22193,7 +22193,7 @@
 (define_insn "loadddup"
   [(set (match_operand:V2DF 0 "register_operand" "=x")
        (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "movddup\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "mode" "DF")])
@@ -22203,7 +22203,7 @@
        (vec_duplicate:V2DF
         (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
                        (parallel [(const_int 0)]))))]
-  "TARGET_PNI"
+  "TARGET_SSE3"
   "movddup\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "mode" "DF")])
diff --git a/gcc/config/i386/pmmintrin.h b/gcc/config/i386/pmmintrin.h
index 5649c00d6730f6e403d9f828a77535c0b659d829..f42076bb9c1680f8e228824b2e10485d0c88f89b 100644 (file)
--- a/gcc/config/i386/pmmintrin.h
+++ b/gcc/config/i386/pmmintrin.h
@@ -30,7 +30,7 @@
 #ifndef _PMMINTRIN_H_INCLUDED
 #define _PMMINTRIN_H_INCLUDED
 
-#ifdef __PNI__
+#ifdef __SSE3__
 #include <xmmintrin.h>
 #include <emmintrin.h>
 
@@ -127,6 +127,6 @@ _mm_mwait (unsigned int __E, unsigned int __H)
 #define _mm_mwait(E, H)                __builtin_ia32_mwait ((E), (H))
 #endif
 
-#endif /* __PNI__ */
+#endif /* __SSE3__ */
 
 #endif /* _PMMINTRIN_H_INCLUDED */
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 4d587c715f7bb8cfa4961a10cfa786e414e51845..f4fd28ea8e3275dba9adc4f71fade3ab8a08c92b 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -5337,7 +5337,7 @@ Generates the @code{movhps} machine instruction as a store to memory.
 Generates the @code{movlps} machine instruction as a store to memory.
 @end table
 
-The following built-in functions are available when @option{-mpni} is used.
+The following built-in functions are available when @option{-msse3} is used.
 All of them generate the machine instruction that is part of the name.
 
 @example
@@ -5355,7 +5355,7 @@ v4sf __builtin_ia32_movsldup (v4sf)
 void __builtin_ia32_mwait (unsigned int, unsigned int)
 @end example
 
-The following built-in functions are available when @option{-mpni} is used.
+The following built-in functions are available when @option{-msse3} is used.
 
 @table @code
 @item v2df __builtin_ia32_loadddup (double const *)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 615fd13e9c8963a564a0d4b803f09f2b6a49ed1c..00ba3a3fc8b2f8ac40206126e64f7eafa70999cb 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -473,7 +473,7 @@ in the following sections.
 -mno-fp-ret-in-387  -msoft-float  -msvr3-shlib @gol
 -mno-wide-multiply  -mrtd  -malign-double @gol
 -mpreferred-stack-boundary=@var{num} @gol
--mmmx  -msse  -msse2 -mpni -m3dnow @gol
+-mmmx  -msse  -msse2 -msse3 -m3dnow @gol
 -mthreads  -mno-align-stringops  -minline-all-stringops @gol
 -mpush-args  -maccumulate-outgoing-args  -m128bit-long-double @gol
 -m96bit-long-double  -mregparm=@var{num}  -momit-leaf-frame-pointer @gol
@@ -8092,8 +8092,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @itemx -mno-sse
 @item -msse2
 @itemx -mno-sse2
-@item -mpni
-@itemx -mno-pni
+@item -msse3
+@itemx -mno-sse3
 @item -m3dnow
 @itemx -mno-3dnow
 @opindex mmmx
@@ -8103,7 +8103,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @opindex m3dnow
 @opindex mno-3dnow
 These switches enable or disable the use of built-in functions that allow
-direct access to the MMX, SSE and 3Dnow extensions of the instruction set.
+direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
+instruction set.
 
 @xref{X86 Built-in Functions}, for details of the functions enabled
 and disabled by these switches.
Mirror of https://gcc.gnu.org/git/gcc.git