drm/i915/display: Add DC Balance flip count operations

Track dc balance flip count with params per crtc. Increment
DC Balance Flip count before every flip to indicate DMC
firmware about new flip occurrence which needs to be adjusted
for dc balancing. This is tracked separately from legacy
FLIP_COUNT register also Reset DC balance flip count value
while disabling VRR adaptive mode, this is to start with
fresh counts when VRR adaptive refresh mode is triggered again.

--v2:
- Call during intel_update_crtc.(Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-11-mitulkumar.ajitkumar.golani@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 35a97d6bc059b05f7749cd723647432722efc1cb..68e67dc2631f83d7176be76992c34fc971882317 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6864,6 +6864,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
                intel_crtc_update_active_timings(new_crtc_state,
                                                 new_crtc_state->vrr.enable);
 
+       if (new_crtc_state->vrr.dc_balance.enable)
+               intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
+
        /*
         * We usually enable FIFO underrun interrupts as part of the
         * CRTC enable sequence during modesets.  But when we inherit a

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 75acfe043997fb6092332a8a47816eaa5edbb4f3..113e43bc1f6df3e62ce677f0574a455e06ab2b2e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1531,6 +1531,10 @@ struct intel_crtc {
                struct intel_link_m_n m_n, m2_n2;
        } drrs;
 
+       struct {
+               u64 flip_count;
+       } dc_balance;
+
        int scanline_offset;
 
        struct {

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c3a8161fb8e15b1762f37f95c5195db1965311c6..92be789a65009dd2b58358cde3171f815b7bb1a7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -646,6 +646,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
                               EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
 }
 
+void
+intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+                                  struct intel_crtc *crtc)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       enum pipe pipe = crtc->pipe;
+
+       if (!crtc_state->vrr.dc_balance.enable)
+               return;
+
+       intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
+                      ++crtc->dc_balance.flip_count);
+}
+
 void
 intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
                    struct intel_crtc *crtc)
@@ -656,6 +670,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
        if (!old_crtc_state->vrr.dc_balance.enable)
                return;
 
+       intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
        intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index d40ed5504180247621b3c6e3bccde12838329834..bedcc8c4bff2f4ac3fc666b8825f7618ca6f0998 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -29,6 +29,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
                         const struct intel_crtc_state *crtc_state);
 void intel_vrr_check_push_sent(struct intel_dsb *dsb,
                               const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+                                       struct intel_crtc *crtc);
 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state);