]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: amlogic: move CPU OPP table and clock assignment to SoC.dtsi
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Fri, 9 Jan 2026 21:02:17 +0000 (22:02 +0100)
committerNeil Armstrong <neil.armstrong@linaro.org>
Tue, 13 Jan 2026 07:59:27 +0000 (08:59 +0100)
Move the assignment of the CPU clocks and the CPU OPP table(s) from
board.dts to SoC.dtsi to reduce the code duplication.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260109210217.828961-1-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
24 files changed:
arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi

index d0a3b4b9229cc60394fe122fa1124a135866e0d6..abf6b63ea0d7ba8d72dbeb03f569cffb14412a3a 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &ethmac {
index 4353485c6f26b98eeeb37d8dfb3964c906b80f8e..a85f383a169962c82372d33dd70d3f0256f56f08 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cvbs_vdac_port {
index f39fcabc763f1ab1e22cf38e7766e12e42c046e6..5b6716aeaae5c304a1caa1426dd0073533e03869 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cvbs_vdac_port {
index b5bf8ecc91e653e4a4082c5a4d17dba8239dbf47..dd9da7a5ec5ff04feb74f86b6338477a8a27256d 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &clkc_audio {
index 5ab460a3e637f714fe38f9b4ad106198c1709d5a..015e3c7e3a919e7f1b5e220bb172062389142acd 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cvbs_vdac_port {
index 1321ad95923d2c2bf0649214ddee30e14476a1ac..51317d11f263b1f01ca773ce32a264488bfd9997 100644 (file)
@@ -25,6 +25,8 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU_CLK>;
                };
 
                cpu1: cpu@1 {
@@ -40,6 +42,8 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU_CLK>;
                };
 
                cpu2: cpu@2 {
@@ -55,6 +59,8 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU_CLK>;
                };
 
                cpu3: cpu@3 {
@@ -70,6 +76,8 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU_CLK>;
                };
 
                l2: l2-cache0 {
index 82546b73897716d4fe045207b710a76b3859aed2..5747acf8f337cd76b857b1921ea6f2c58232efa6 100644 (file)
@@ -6,7 +6,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/clock/g12a-clkc.h>
 #include "meson-g12b-a311d.dtsi"
 #include "meson-libretech-cottonwood.dtsi"
 
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &pwm_ab {
index 8ecb5bd125c1a4729c63d7f2b3edb4a2fecef5eb..f15baa708b36873ca286858e70c87f4e2e5d27b7 100644 (file)
                 };
        };
 };
+
+&cpu0 {
+       operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu1 {
+       operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu100 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu101 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu102 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu103 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
index 39011b645128cb9ee1107f4731d56840f2bdf5a7..7a204d324dd4fb3614402d94324e906cf08650b5 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &ext_mdio {
index 1b08303c42822ba94f600ef6e19ca057bf5fe7ed..4321d08d11a6acbf0b0a2b9d9db48cedd22947ba 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &ethmac {
index fc737499f207aa7c873371de5a59ca2a70e7c24b..b16247e0df9fb5ea92a351d4d196ac8a8a71e2c2 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &pwm_ab {
index d5938a4a6da375e5fbff89c761e634e7b85775fe..c81d7fdbe2f5da7c9f6c489f833334ffbe4bcd33 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 /* RK817 only supports 12.5mV steps, round up the values */
index 3298d59833b643d2e925c80dc20778210ac937a5..88d995006f94eb642b114e5616d2389e1eba1daf 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu_thermal {
index 1e5c6f98494564aa61c9da269488bd52fd270b6b..e95e193eaebc7b77f7c7bbeb484beda3c35b0975 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu_thermal {
index 19cad93a68897ca00856983a936409d36786b3e4..eef98add05c6b47ae1182abb9ce87816cfa07292 100644 (file)
                };
        };
 };
+
+&cpu0 {
+       operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu1 {
+       operating-points-v2 = <&cpu_opp_table_0>;
+};
+
+&cpu100 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu101 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu102 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
+
+&cpu103 {
+       operating-points-v2 = <&cpub_opp_table_1>;
+};
index 9b6d780eada777a8314c9877f75c635076404c01..4834f418bef58dccd81c893bfe23d2c454b8603a 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table_0>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu100 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu101 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu102 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cpu103 {
        cpu-supply = <&vddcpu_a>;
-       operating-points-v2 = <&cpub_opp_table_1>;
-       clocks = <&clkc CLKID_CPUB_CLK>;
 };
 
 &cvbs_vdac_port {
index 23358d94844c94539c82bfabf0d5c990afab99d8..18506d54d2393fced7be5d487fa88535872bbd38 100644 (file)
@@ -57,6 +57,7 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2_cache_l>;
                        #cooling-cells = <2>;
+                       clocks = <&clkc CLKID_CPU_CLK>;
                };
 
                cpu1: cpu@1 {
@@ -73,6 +74,7 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2_cache_l>;
                        #cooling-cells = <2>;
+                       clocks = <&clkc CLKID_CPU_CLK>;
                };
 
                cpu100: cpu@100 {
@@ -89,6 +91,7 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
+                       clocks = <&clkc CLKID_CPUB_CLK>;
                };
 
                cpu101: cpu@101 {
                        i-cache-sets = <32>;
                        next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
+                       clocks = <&clkc CLKID_CPUB_CLK>;
                };
 
                cpu102: cpu@102 {
                        i-cache-sets = <64>;
                        next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
+                       clocks = <&clkc CLKID_CPUB_CLK>;
                };
 
                cpu103: cpu@103 {
                        i-cache-sets = <64>;
                        next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpub_opp_table_1>;
+                       clocks = <&clkc CLKID_CPUB_CLK>;
                };
 
                l2_cache_l: l2-cache-cluster0 {
index 9be3084b090d2441098d97155e8d56d54560799b..661e454ca6731c0dd52a10c208547a89a2b5f8ee 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU1_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU2_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU3_CLK>;
 };
 
 &cvbs_vdac_port {
index 5e07f0f9538e542737f7448fb0a19c9243c8f3b3..f0e4b168a41126512a4574f0b28ca303fe57b28b 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU1_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU2_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU3_CLK>;
 };
 
 &ext_mdio {
index a3d9b66b6878fb2744e8dc31a95c53fa837613e1..4e1e9a5026666e506d888d62e1b97ec6d04d09a6 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU1_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU2_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU3_CLK>;
 };
 
 &pwm_AO_cd {
index c4524eb4f0996dfbccec16ca5b936a5c3b2663a5..ad886d446e96e314692cdca8cc384a10bde6295e 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU1_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU2_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU3_CLK>;
 };
 
 &ext_mdio {
index 5daadfb170b42cc52f74052593218fc0c6709053..2a16f54332df3a544dda4f29ece3ea460f881249 100644 (file)
@@ -6,7 +6,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/clock/g12a-clkc.h>
 #include "meson-sm1.dtsi"
 #include "meson-libretech-cottonwood.dtsi"
 
 
 &cpu0 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU1_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU2_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu_b>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU3_CLK>;
 };
index 024d2eb8e6ee0f6a198cd70f144dfd0a0b26fa61..e275b0f36b0950775c83d13c50b726bbc9dfa879 100644 (file)
 
 &cpu0 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU_CLK>;
 };
 
 &cpu1 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU1_CLK>;
 };
 
 &cpu2 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU2_CLK>;
 };
 
 &cpu3 {
        cpu-supply = <&vddcpu>;
-       operating-points-v2 = <&cpu_opp_table>;
-       clocks = <&clkc CLKID_CPU3_CLK>;
 };
 
 &ethmac {
index e5db8ce940620c25a4293f328c93e1237b821d41..8f5b850b1774f184396b8434507ec6169446e30b 100644 (file)
@@ -63,6 +63,8 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU_CLK>;
                };
 
                cpu1: cpu@1 {
@@ -78,6 +80,8 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU1_CLK>;
                };
 
                cpu2: cpu@2 {
@@ -93,6 +97,8 @@
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU2_CLK>;
                };
 
                cpu3: cpu@3 {
                        i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
+                       operating-points-v2 = <&cpu_opp_table>;
+                       clocks = <&clkc CLKID_CPU3_CLK>;
                };
 
                l2: l2-cache0 {