arm: [MVE intrinsics] factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq

Factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq so that they use the
same pattern.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VMAXNMxV_MINNMxVQ)
	(MVE_VMAXNMxV_MINNMxVQ_P): New.
	(mve_insn): Add vmaxnmav, vmaxnmv, vminnmav, vminnmv.
	* config/arm/mve.md (mve_vmaxnmavq_f<mode>, mve_vmaxnmvq_f<mode>)
	(mve_vminnmavq_f<mode>, mve_vminnmvq_f<mode>): Merge into ...
	(@mve_<mve_insn>q_f<mode>): ... this.
	(mve_vmaxnmavq_p_f<mode>, mve_vmaxnmvq_p_f<mode>)
	(mve_vminnmavq_p_f<mode>, mve_vminnmvq_p_f<mode>): Merge into ...
	(@mve_<mve_insn>q_p_f<mode>): ... this.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 397ac32720d690ca8522e065d18641745f02d8da..26ad687cefd62804e4d552a27e33e0e8cfeac342 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -597,6 +597,20 @@
                     VMINVQ_P_S VMINVQ_P_U
                     ])
 
+(define_int_iterator MVE_VMAXNMxV_MINNMxVQ [
+                    VMAXNMAVQ_F
+                    VMAXNMVQ_F
+                    VMINNMAVQ_F
+                    VMINNMVQ_F
+                    ])
+
+(define_int_iterator MVE_VMAXNMxV_MINNMxVQ_P [
+                    VMAXNMAVQ_P_F
+                    VMAXNMVQ_P_F
+                    VMINNMAVQ_P_F
+                    VMINNMVQ_P_F
+                    ])
+
 (define_int_iterator MVE_MOVN [
                     VMOVNBQ_S VMOVNBQ_U
                     VMOVNTQ_S VMOVNTQ_U
@@ -648,13 +662,21 @@
                 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
                 (VMAXAVQ_P_S "vmaxav")
                 (VMAXAVQ_S "vmaxav")
+                (VMAXNMAVQ_F "vmaxnmav")
+                (VMAXNMAVQ_P_F "vmaxnmav")
                 (VMAXNMQ_M_F "vmaxnm")
+                (VMAXNMVQ_F "vmaxnmv")
+                (VMAXNMVQ_P_F "vmaxnmv")
                 (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
                 (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
                 (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
                 (VMINAVQ_P_S "vminav")
                 (VMINAVQ_S "vminav")
+                (VMINNMAVQ_F "vminnmav")
+                (VMINNMAVQ_P_F "vminnmav")
                 (VMINNMQ_M_F "vminnm")
+                (VMINNMVQ_F "vminnmv")
+                (VMINNMVQ_P_F "vminnmv")
                 (VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
                 (VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv")
                 (VMINVQ_S "vminv") (VMINVQ_U "vminv")

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index d2863b316e0ca9d6b261104b4d6d1e5c2aa45991..2aebaa99bbf129d3eca1b8832118e7ddc06a63cb 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1440,17 +1440,20 @@
 ])
 
 ;;
-;; [vmaxnmavq_f])
+;; [vmaxnmavq_f]
+;; [vmaxnmvq_f]
+;; [vminnmavq_f]
+;; [vminnmvq_f]
 ;;
-(define_insn "mve_vmaxnmavq_f<mode>"
+(define_insn "@mve_<mve_insn>q_f<mode>"
   [
    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
        (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
                          (match_operand:MVE_0 2 "s_register_operand" "w")]
-        VMAXNMAVQ_F))
+        MVE_VMAXNMxV_MINNMxVQ))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmaxnmav.f%#<V_sz_elem>     %0, %q2"
+  "<mve_insn>.f%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1469,21 +1472,6 @@
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vmaxnmvq_f])
-;;
-(define_insn "mve_vmaxnmvq_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-       (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-                         (match_operand:MVE_0 2 "s_register_operand" "w")]
-        VMAXNMVQ_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vmaxnmv.f%#<V_sz_elem>      %0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vminnmaq_f])
 ;;
@@ -1499,36 +1487,6 @@
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vminnmavq_f])
-;;
-(define_insn "mve_vminnmavq_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-       (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-                         (match_operand:MVE_0 2 "s_register_operand" "w")]
-        VMINNMAVQ_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vminnmav.f%#<V_sz_elem>     %0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vminnmvq_f])
-;;
-(define_insn "mve_vminnmvq_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-       (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-                         (match_operand:MVE_0 2 "s_register_operand" "w")]
-        VMINNMVQ_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vminnmv.f%#<V_sz_elem>      %0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vmlaldavq_u, vmlaldavq_s])
 ;;
@@ -3202,37 +3160,26 @@
   "vpst\;vmaxnmat.f%#<V_sz_elem>       %q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
-;;
-;; [vmaxnmavq_p_f])
-;;
-(define_insn "mve_vmaxnmavq_p_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-       (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-                      (match_operand:MVE_0 2 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMAXNMAVQ_P_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vmaxnmavt.f%#<V_sz_elem>      %0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
 
 ;;
-;; [vmaxnmvq_p_f])
+;; [vmaxnmavq_p_f]
+;; [vmaxnmvq_p_f]
+;; [vminnmavq_p_f]
+;; [vminnmvq_p_f]
 ;;
-(define_insn "mve_vmaxnmvq_p_f<mode>"
+(define_insn "@mve_<mve_insn>q_p_f<mode>"
   [
    (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
        (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
                       (match_operand:MVE_0 2 "s_register_operand" "w")
                       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMAXNMVQ_P_F))
+        MVE_VMAXNMxV_MINNMxVQ_P))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vmaxnmvt.f%#<V_sz_elem>       %0, %q2"
+  "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
+
 ;;
 ;; [vminnmaq_m_f])
 ;;
@@ -3249,37 +3196,6 @@
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vminnmavq_p_f])
-;;
-(define_insn "mve_vminnmavq_p_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-       (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-                      (match_operand:MVE_0 2 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMINNMAVQ_P_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vminnmavt.f%#<V_sz_elem>      %0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-;;
-;; [vminnmvq_p_f])
-;;
-(define_insn "mve_vminnmvq_p_f<mode>"
-  [
-   (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
-       (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
-                      (match_operand:MVE_0 2 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-        VMINNMVQ_P_F))
-  ]
-  "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
-  "vpst\;vminnmvt.f%#<V_sz_elem>       %0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vmlaldavaq_s, vmlaldavaq_u])
 ;;