arm64: dts: s32g: add the pinctrl node

Add the pinctrl node in the device tree in order to enable the
S32G2/S32G3 pinctrl driver to probe.

Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index fc19ae2e8d3bc4b2e40bc34bcbe402782f4e77ca..fa054bfe7d5c556046050ce9a6edbc02b29b789c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -114,6 +114,56 @@
                #size-cells = <1>;
                ranges = <0 0 0 0x80000000>;
 
+               pinctrl: pinctrl@4009c240 {
+                       compatible = "nxp,s32g2-siul2-pinctrl";
+                               /* MSCR0-MSCR101 registers on siul2_0 */
+                       reg = <0x4009c240 0x198>,
+                               /* MSCR112-MSCR122 registers on siul2_1 */
+                             <0x44010400 0x2c>,
+                               /* MSCR144-MSCR190 registers on siul2_1 */
+                             <0x44010480 0xbc>,
+                               /* IMCR0-IMCR83 registers on siul2_0 */
+                             <0x4009ca40 0x150>,
+                               /* IMCR119-IMCR397 registers on siul2_1 */
+                             <0x44010c1c 0x45c>,
+                               /* IMCR430-IMCR495 registers on siul2_1 */
+                             <0x440110f8 0x108>;
+
+                       jtag_pins: jtag-pins {
+                               jtag-grp0 {
+                                       pinmux = <0x0>;
+                                       input-enable;
+                                       bias-pull-up;
+                                       slew-rate = <166>;
+                               };
+
+                               jtag-grp1 {
+                                       pinmux = <0x11>;
+                                       slew-rate = <166>;
+                               };
+
+                               jtag-grp2 {
+                                       pinmux = <0x40>;
+                                       input-enable;
+                                       bias-pull-down;
+                                       slew-rate = <166>;
+                               };
+
+                               jtag-grp3 {
+                                       pinmux = <0x23c0>,
+                                                <0x23d0>,
+                                                <0x2320>;
+                               };
+
+                               jtag-grp4 {
+                                       pinmux = <0x51>;
+                                       input-enable;
+                                       bias-pull-up;
+                                       slew-rate = <166>;
+                               };
+                       };
+               };
+
                uart0: serial@401c8000 {
                        compatible = "nxp,s32g2-linflexuart",
                                     "fsl,s32v234-linflexuart";

diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index c1b08992754b0c877f9eba5dd231682546de849c..b4226a9143c80eeb396dd625c7806ed4bad58159 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2021-2023 NXP
+ * Copyright 2021-2024 NXP
  *
  * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
  *          Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -171,6 +171,56 @@
                #size-cells = <1>;
                ranges = <0 0 0 0x80000000>;
 
+               pinctrl: pinctrl@4009c240 {
+                       compatible = "nxp,s32g2-siul2-pinctrl";
+                               /* MSCR0-MSCR101 registers on siul2_0 */
+                       reg = <0x4009c240 0x198>,
+                               /* MSCR112-MSCR122 registers on siul2_1 */
+                             <0x44010400 0x2c>,
+                               /* MSCR144-MSCR190 registers on siul2_1 */
+                             <0x44010480 0xbc>,
+                               /* IMCR0-IMCR83 registers on siul2_0 */
+                             <0x4009ca40 0x150>,
+                               /* IMCR119-IMCR397 registers on siul2_1 */
+                             <0x44010c1c 0x45c>,
+                               /* IMCR430-IMCR495 registers on siul2_1 */
+                             <0x440110f8 0x108>;
+
+                       jtag_pins: jtag-pins {
+                               jtag-grp0 {
+                                       pinmux = <0x0>;
+                                       input-enable;
+                                       bias-pull-up;
+                                       slew-rate = <166>;
+                               };
+
+                               jtag-grp1 {
+                                       pinmux = <0x11>;
+                                       slew-rate = <166>;
+                               };
+
+                               jtag-grp2 {
+                                       pinmux = <0x40>;
+                                       input-enable;
+                                       bias-pull-down;
+                                       slew-rate = <166>;
+                               };
+
+                               jtag-grp3 {
+                                       pinmux = <0x23c0>,
+                                                <0x23d0>,
+                                                <0x2320>;
+                               };
+
+                               jtag-grp4 {
+                                       pinmux = <0x51>;
+                                       input-enable;
+                                       bias-pull-up;
+                                       slew-rate = <166>;
+                               };
+                       };
+               };
+
                uart0: serial@401c8000 {
                        compatible = "nxp,s32g3-linflexuart",
                                     "fsl,s32v234-linflexuart";