PCI: imx6: Add external reference clock input mode support

i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator.

Add external reference clock input mode support for i.MX95 PCIes.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251211064821.2707001-4-hongxing.zhu@nxp.com

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 4668fc9648bff637c779e2f4d5f182671348258c..a6db1f0f73c3603bddc4fce248e82c7c9e599a83 100644 (file)
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -149,6 +149,7 @@ struct imx_pcie {
        struct gpio_desc        *reset_gpiod;
        struct clk_bulk_data    *clks;
        int                     num_clks;
+       bool                    enable_ext_refclk;
        struct regmap           *iomuxc_gpr;
        u16                     msi_ctrl;
        u32                     controller_id;
@@ -241,6 +242,8 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
+       bool ext = imx_pcie->enable_ext_refclk;
+
        /*
         * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
         * Through Beacon or PERST# De-assertion
@@ -259,13 +262,12 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
                        IMX95_PCIE_PHY_CR_PARA_SEL,
                        IMX95_PCIE_PHY_CR_PARA_SEL);
 
-       regmap_update_bits(imx_pcie->iomuxc_gpr,
-                          IMX95_PCIE_PHY_GEN_CTRL,
-                          IMX95_PCIE_REF_USE_PAD, 0);
-       regmap_update_bits(imx_pcie->iomuxc_gpr,
-                          IMX95_PCIE_SS_RW_REG_0,
+       regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+                          ext ? IMX95_PCIE_REF_USE_PAD : 0,
+                          IMX95_PCIE_REF_USE_PAD);
+       regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
                           IMX95_PCIE_REF_CLKEN,
-                          IMX95_PCIE_REF_CLKEN);
+                          ext ? 0 : IMX95_PCIE_REF_CLKEN);
 
        return 0;
 }
@@ -1602,7 +1604,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
        struct imx_pcie *imx_pcie;
        struct device_node *np;
        struct device_node *node = dev->of_node;
-       int ret, domain;
+       int i, ret, domain;
        u16 val;
 
        imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
@@ -1653,6 +1655,9 @@ static int imx_pcie_probe(struct platform_device *pdev)
        if (imx_pcie->num_clks < 0)
                return dev_err_probe(dev, imx_pcie->num_clks,
                                     "failed to get clocks\n");
+       for (i = 0; i < imx_pcie->num_clks; i++)
+               if (strncmp(imx_pcie->clks[i].id, "extref", 6) == 0)
+                       imx_pcie->enable_ext_refclk = true;
 
        if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
                imx_pcie->phy = devm_phy_get(dev, "pcie-phy");