arm64: update comment for DCZID_EL0

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 0d95ad73ccade3302779f239896a2ed870d88daf..79a53cdcb67fb93cc103581f04b04aa3f28a6a33 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -7884,8 +7884,8 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
    }
    /* ---- Cases for DCZID_EL0 ----
       This is the data cache zero ID register. It controls whether
-      DC ZVA is supported and if so the block size used. Support reads of it
-      only by passing through to the host.
+      DC ZVA is supported and if so the block size used. Use the values
+      read during startup when calling get_cache_info.
       D5 3B 00 111 Rt  MRS rT, dczid_el0
    */
    if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53B00E0) {