clk: renesas: r8a779g0: Add ISP core clocks

Add the ISP core modules clock for Renesas R-Car V4H.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250114183005.2761213-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index d45571096b963b2e204e5d6b9426b664369cb942..015b9773cc55f0aa94e392aa52b38f2d7934ec9b 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -163,6 +163,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
+       DEF_MOD("isp0",          16,    R8A779G0_CLK_S0D2_VIO),
+       DEF_MOD("isp1",          17,    R8A779G0_CLK_S0D2_VIO),
        DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb1",         212,    R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("avb2",         213,    R8A779G0_CLK_S0D4_HSC),