clk: renesas: r9a09g056: Add entries for the RSPIs

Add clock and reset entries for the RSPI IPs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251125221420.288809-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 1c6228b0544e75ae258de53b87be82a2d190a4d2..4b068199edde476a0aef38e16631dd53501be4fb 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -281,6 +281,24 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(5, BIT(13))),
        DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
                                                BUS_MSTOP(5, BIT(13))),
+       DEF_MOD("rspi_0_pclk",                  CLK_PLLCLN_DIV8, 5, 4, 2, 20,
+                                               BUS_MSTOP(11, BIT(0))),
+       DEF_MOD("rspi_0_pclk_sfr",              CLK_PLLCLN_DIV8, 5, 5, 2, 21,
+                                               BUS_MSTOP(11, BIT(0))),
+       DEF_MOD("rspi_0_tclk",                  CLK_PLLCLN_DIV8, 5, 6, 2, 22,
+                                               BUS_MSTOP(11, BIT(0))),
+       DEF_MOD("rspi_1_pclk",                  CLK_PLLCLN_DIV8, 5, 7, 2, 23,
+                                               BUS_MSTOP(11, BIT(1))),
+       DEF_MOD("rspi_1_pclk_sfr",              CLK_PLLCLN_DIV8, 5, 8, 2, 24,
+                                               BUS_MSTOP(11, BIT(1))),
+       DEF_MOD("rspi_1_tclk",                  CLK_PLLCLN_DIV8, 5, 9, 2, 25,
+                                               BUS_MSTOP(11, BIT(1))),
+       DEF_MOD("rspi_2_pclk",                  CLK_PLLCLN_DIV8, 5, 10, 2, 26,
+                                               BUS_MSTOP(11, BIT(2))),
+       DEF_MOD("rspi_2_pclk_sfr",              CLK_PLLCLN_DIV8, 5, 11, 2, 27,
+                                               BUS_MSTOP(11, BIT(2))),
+       DEF_MOD("rspi_2_tclk",                  CLK_PLLCLN_DIV8, 5, 12, 2, 28,
+                                               BUS_MSTOP(11, BIT(2))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
        DEF_MOD("i3c_0_pclkrw",                 CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -437,6 +455,12 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(7, 6, 3, 7),            /* WDT_1_RESET */
        DEF_RST(7, 7, 3, 8),            /* WDT_2_RESET */
        DEF_RST(7, 8, 3, 9),            /* WDT_3_RESET */
+       DEF_RST(7, 11, 3, 12),          /* RSPI_0_PRESETN */
+       DEF_RST(7, 12, 3, 13),          /* RSPI_0_TRESETN */
+       DEF_RST(7, 13, 3, 14),          /* RSPI_1_PRESETN */
+       DEF_RST(7, 14, 3, 15),          /* RSPI_1_TRESETN */
+       DEF_RST(7, 15, 3, 16),          /* RSPI_2_PRESETN */
+       DEF_RST(8, 0, 3, 17),           /* RSPI_2_TRESETN */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
        DEF_RST(9, 6, 4, 7),            /* I3C_0_PRESETN */
        DEF_RST(9, 7, 4, 8),            /* I3C_0_TRESETN */