drm/msm/a6xx: Improve MX rail fallback in RPMH vote init

[ Upstream commit ca04ce7a2f22652fdf6489fa7e02e7d2c08698f4 ]

Current logic assumes that the voltage corners in both MxG and MxA are
always same. This is not true for recent targets. So, rework the rpmh init
sequence to probe and calculate the votes with the respective rails, ie,
GX rails should use MxG as secondary rail and Cx rail should use MxA as
the secondary rail.

Fixes: d6225e0cd096 ("drm/msm/adreno: Add support for X185 GPU")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689014/
Message-ID: <20251118-kaana-gpu-support-v4-12-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 605bb55de8d529f8644f44ea911d00ac1ef0999e..21a3f9b0ab4c2536a040d0cc48efeeaa3f6f2caa 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1492,13 +1492,14 @@ static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
 }
 
 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
-               unsigned long *freqs, int freqs_count, const char *id)
+               unsigned long *freqs, int freqs_count,
+               const char *pri_id, const char *sec_id)
 {
        int i, j;
        const u16 *pri, *sec;
        size_t pri_count, sec_count;
 
-       pri = cmd_db_read_aux_data(id, &pri_count);
+       pri = cmd_db_read_aux_data(pri_id, &pri_count);
        if (IS_ERR(pri))
                return PTR_ERR(pri);
        /*
@@ -1509,13 +1510,7 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
        if (!pri_count)
                return -EINVAL;
 
-       /*
-        * Some targets have a separate gfx mxc rail. So try to read that first and then fall back
-        * to regular mx rail if it is missing
-        */
-       sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count);
-       if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER))
-               sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
+       sec = cmd_db_read_aux_data(sec_id, &sec_count);
        if (IS_ERR(sec))
                return PTR_ERR(sec);
 
@@ -1583,15 +1578,24 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
        const struct a6xx_info *info = adreno_gpu->info->a6xx;
        struct msm_gpu *gpu = &adreno_gpu->base;
+       const char *sec_id;
+       const u16 *gmxc;
        int ret;
 
+       gmxc = cmd_db_read_aux_data("gmxc.lvl", NULL);
+       if (gmxc == ERR_PTR(-EPROBE_DEFER))
+               return -EPROBE_DEFER;
+
+       /* If GMxC is present, prefer that as secondary rail for GX votes */
+       sec_id = IS_ERR_OR_NULL(gmxc) ? "mx.lvl" : "gmxc.lvl";
+
        /* Build the GX votes */
        ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
-               gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
+               gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl", sec_id);
 
        /* Build the CX votes */
        ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
-               gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
+               gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl");
 
        /* Build the interconnect votes */
        if (info->bcms && gmu->nr_gpu_bws > 1)