drm/msm/adreno: rename llc_mmio to cx_misc_mmio

This region is used for more than just LLCC, it also provides access to
software fuse values (raytracing, etc).

Rename relevant symbols from _llc to _cx_misc for use in a follow up
change that decouples this from LLCC.

Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Patchwork: https://patchwork.freedesktop.org/patch/728806/
Message-ID: <20260528-adreno-810-v7-3-7fe7fdd97fc2@pm.me>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 47b5702e1b40d216d9039cec74e549d086b8f02b..2e5d7b53a0c380c664a1bd66eb7e51be8a151b93 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -947,7 +947,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
 
        /* Turn on TCM (Tightly Coupled Memory) retention */
        if (adreno_is_a7xx(adreno_gpu))
-               a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
+               a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
        else if (!adreno_is_a8xx(adreno_gpu))
                gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
 
@@ -1215,7 +1215,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
                if (!qcom_scm_is_available()) {
                        dev_warn_once(gpu->dev->dev,
                                "SCM is not available, poking fuse register\n");
-                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                       a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
                                A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
                                A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
                                A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
@@ -1236,7 +1236,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
                 * firmware, find out whether that's the case. The scm call
                 * above sets the fuse register.
                 */
-               fuse_val = a6xx_llc_read(a6xx_gpu,
+               fuse_val = a6xx_cx_misc_read(a6xx_gpu,
                                         REG_A7XX_CX_MISC_SW_FUSE_VALUE);
                adreno_gpu->has_ray_tracing =
                        !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
@@ -1343,7 +1343,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 
        /* Check to see if we are doing a cold or warm boot */
        if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
-               status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
+               status = a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
                        GMU_WARM_BOOT : GMU_COLD_BOOT;
        } else if (gmu->legacy) {
                status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 4bb3be3ff9d0e5711f1c348334c70368ae75cbe9..a65dc653ca732cf15c0fb40cff30c4a9da5734b7 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1961,7 +1961,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
        struct msm_gpu *gpu = &adreno_gpu->base;
        u32 cntl1_regval = 0;
 
-       if (IS_ERR(a6xx_gpu->llc_mmio))
+       if (IS_ERR(a6xx_gpu->cx_misc_mmio))
                return;
 
        if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
@@ -2000,14 +2000,14 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
         * pagetables
         */
        if (!a6xx_gpu->have_mmu500) {
-               a6xx_llc_write(a6xx_gpu,
+               a6xx_cx_misc_write(a6xx_gpu,
                        REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
 
                /*
                 * Program cacheability overrides to not allocate cache
                 * lines on a write miss
                 */
-               a6xx_llc_rmw(a6xx_gpu,
+               a6xx_cx_misc_rmw(a6xx_gpu,
                        REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
                return;
        }
@@ -2020,7 +2020,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
        struct msm_gpu *gpu = &adreno_gpu->base;
 
-       if (IS_ERR(a6xx_gpu->llc_mmio))
+       if (IS_ERR(a6xx_gpu->cx_misc_mmio))
                return;
 
        if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
@@ -2073,15 +2073,15 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
        of_node_put(phandle);
 
        if (is_a7xx || !a6xx_gpu->have_mmu500)
-               a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem");
+               a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem");
        else
-               a6xx_gpu->llc_mmio = NULL;
+               a6xx_gpu->cx_misc_mmio = NULL;
 
        a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
        a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
 
        if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
-               a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
+               a6xx_gpu->cx_misc_mmio = ERR_PTR(-EINVAL);
 }
 
 #define GBIF_CLIENT_HALT_MASK          BIT(0)
@@ -2618,7 +2618,7 @@ static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,
                return ret;
 
        if (info->quirks & ADRENO_QUIRK_SOFTFUSE) {
-               *speedbin = a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
+               *speedbin = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
                *speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin);
                return 0;
        }

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index f60a0801a62d7c38c8699fc7b8ec918e32f9fc96..b50c57f427b44d78ba2e1b781aca9acebb406475 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -112,7 +112,7 @@ struct a6xx_gpu {
 
        bool has_whereami;
 
-       void __iomem *llc_mmio;
+       void __iomem *cx_misc_mmio;
        void *llc_slice;
        void *htw_llc_slice;
        bool have_mmu500;
@@ -250,19 +250,19 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
        return true;
 }
 
-static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
+static inline void a6xx_cx_misc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
 {
-       return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
+       return msm_rmw(a6xx_gpu->cx_misc_mmio + (reg << 2), mask, or);
 }
 
-static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
+static inline u32 a6xx_cx_misc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
 {
-       return readl(a6xx_gpu->llc_mmio + (reg << 2));
+       return readl(a6xx_gpu->cx_misc_mmio + (reg << 2));
 }
 
-static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
+static inline void a6xx_cx_misc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
 {
-       writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+       writel(value, a6xx_gpu->cx_misc_mmio + (reg << 2));
 }
 
 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index abe100d9aeaa8a570d6f5faab793e8ca70f43080..c3492e2705ce35ec79bdcdd478c0ae8dfa3c74bb 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -104,7 +104,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu)
                return;
        }
 
-       slice_mask &= a6xx_llc_read(a6xx_gpu,
+       slice_mask &= a6xx_cx_misc_read(a6xx_gpu,
                        REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL);
 
        a6xx_gpu->slice_mask = slice_mask;