dport->dport_dev = dport_dev;
dport->port_id = port_id;
- dport->component_reg_phys = component_reg_phys;
dport->port = port;
cond_cxl_root_lock(port);
* struct cxl_dport - CXL downstream port
* @dport_dev: PCI bridge or firmware device representing the downstream link
* @port_id: unique hardware identifier for dport in decoder target list
- * @component_reg_phys: downstream port component registers
* @rcrb: Data about the Root Complex Register Block layout
* @rch: Indicate whether this dport was enumerated in RCH or VH mode
* @port: reference to cxl_port that contains this downstream port
struct cxl_dport {
struct device *dport_dev;
int port_id;
- resource_size_t component_reg_phys;
struct cxl_rcrb_info rcrb;
bool rch;
struct cxl_port *port;