clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

When a consumer turns on/off a power domain dependent on another power
domain in hardware, the parent power domain shall be turned on/off by
the power domain provider as well, and to get it the power domain hardware
hierarchy shall be described in the CAMCC driver.

Establish the power domain hierarchy with a Titan GDSC set as a parent of
all other GDSC power domains provided by the SM8550 camera clock controller
to enforce a correct sequence of enabling and disabling power domains by
the consumers, this fixes the CAMCC as a supplier of power domains to CAMSS
IP and its driver.

Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20251021234450.2271279-2-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
index 63aed9e4c362d523093409f74ef4e57f292ddf90..b8ece8a57a8a9d86a2dd934be2ebadac28bfbf7e 100644 (file)
--- a/drivers/clk/qcom/camcc-sm8550.c
+++ b/drivers/clk/qcom/camcc-sm8550.c
@@ -3204,6 +3204,8 @@ static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
        },
 };
 
+static struct gdsc cam_cc_titan_top_gdsc;
+
 static struct gdsc cam_cc_bps_gdsc = {
        .gdscr = 0x10004,
        .en_rest_wait_val = 0x2,
@@ -3213,6 +3215,7 @@ static struct gdsc cam_cc_bps_gdsc = {
                .name = "cam_cc_bps_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3225,6 +3228,7 @@ static struct gdsc cam_cc_ife_0_gdsc = {
                .name = "cam_cc_ife_0_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3237,6 +3241,7 @@ static struct gdsc cam_cc_ife_1_gdsc = {
                .name = "cam_cc_ife_1_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3249,6 +3254,7 @@ static struct gdsc cam_cc_ife_2_gdsc = {
                .name = "cam_cc_ife_2_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3261,6 +3267,7 @@ static struct gdsc cam_cc_ipe_0_gdsc = {
                .name = "cam_cc_ipe_0_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3273,6 +3280,7 @@ static struct gdsc cam_cc_sbi_gdsc = {
                .name = "cam_cc_sbi_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3285,6 +3293,7 @@ static struct gdsc cam_cc_sfe_0_gdsc = {
                .name = "cam_cc_sfe_0_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3297,6 +3306,7 @@ static struct gdsc cam_cc_sfe_1_gdsc = {
                .name = "cam_cc_sfe_1_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
+       .parent = &cam_cc_titan_top_gdsc.pd,
        .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };