PCI: xilinx-nwl: Avoid crashing if configuring when the link is down

The ECAM will return a slave error if we access non-root devices while
the link is down. Add a check for this like Linux does so we don't
crash.

Fixes: 2f5ad77cfea ("PCI: zynqmp: Add ZynqMP NWL PCIe root port driver")
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260106220853.731358-1-sean.anderson@linux.dev

diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c
index e03ab3be9128f3ddc785d2ffa01070c10cc57eaf..ab597c83e47b8feaac135d68c9192e26c87e7c23 100644 (file)
--- a/drivers/pci/pcie-xilinx-nwl.c
+++ b/drivers/pci/pcie-xilinx-nwl.c
@@ -135,6 +135,13 @@ struct nwl_pcie {
        u32 ecam_value;
 };
 
+static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
+{
+       if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
+               return true;
+       return false;
+}
+
 static int nwl_pcie_config_address(const struct udevice *bus,
                                   pci_dev_t bdf, uint offset,
                                   void **paddress)
@@ -142,6 +149,9 @@ static int nwl_pcie_config_address(const struct udevice *bus,
        struct nwl_pcie *pcie = dev_get_priv(bus);
        void *addr;
 
+       if (PCI_BUS(bdf) != dev_seq(bus) && !nwl_pcie_link_up(pcie))
+               return -EIO;
+
        addr = pcie->ecam_base;
        addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(bus),
                                 PCI_DEV(bdf), PCI_FUNC(bdf), offset);
@@ -181,13 +191,6 @@ static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
        writel(val, pcie->breg_base + off);
 }
 
-static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
-{
-       if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
-               return true;
-       return false;
-}
-
 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
 {
        if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)